AMD-766AC datasheet(10/96 Pages) AMD

10 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

reset signal from the system keyboard controller. When asserted, an INIT

interrupt to the processor is generated.

LA[23:17]. ISA system address bus bits[23:17]. LA[23:17] and SA[16:0]

combine to for the 24-bit ISA address bus.

Output VDD3

Low

Last

state

LAD[3:0]. LPC address-data bus.

VDD3

3-state 3-state 3-state

LDRQ0# and LDRQ1#. LPC DMA request signals.

Input

VDD3

LFRAME#. LPC frame signal.

VDD3

High

MEMR#. ISA bus memory cycle read command.

Output VDD3

High

MEMW#. ISA bus memory cycle write command.

Output VDD3

High

OSC. 14.31818 MHz. clock. This is used for the programmable interval

timer and various power management timers.

Input

VDD3

ROM_KBCS#. ROM chip select and keyboard chip select. This is

designed to be connected to both the ISA-bus system ROM BIOS and the

keyboard controller. During ISA bus memory accesses this pin decodes

ROM BIOS memory space, as defined by C0A43 (if the ISABIOS pin is

high). During ISA bus IO cycles to the legacy keyboard controller, this

pin decodes accesses to the keyboard controller. The state of this bit is

captured during reset in C3A48[3].

VDD3

Input

High

SA[16:0]. ISA system address bus bits[16:0]. LA[23:17] and SA[16:0]

combine to for the 24-bit ISA address bus.

Output VDD3

Low

Last

state

SD[7:0]. ISA data bus.

IO-PU

VDD3

3-state 3-state 3-state

SPKR. Speaker driver from the programmable interval timer. This pin is

an input while PWRGD is low; it is used to select the default state of

C3A48[ENIDE, ENPCI, ENISA] (the internal pull-up-pull-down IO pin

resister enables).

VDD3

Input

Low

Last

state

3.5

Ultra DMA Enhanced IDE Interface

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

DADDR[P,S][2:0]. IDE controller [primary, secondary] port address.

Output VDD3

Low

DCS1P#. IDE controller primary port chip select 1. This is active during

accesses to the IO address space 1F7h – 1F0h.

Output VDD3

High

DCS1S#. IDE controller secondary port chip select 1. This is active

during accesses to the IO address space 177h – 170h.

Output VDD3

High

DCS3P#. IDE controller primary port chip select 3. This is active during

accesses to the IO address space 3F7h – 3F4h.

Output VDD3

High

DCS3S#. IDE controller secondary port chip select 3. This is active

during accesses to the IO address space 377h – 374h.

Output VDD3

High

DDACK[P,S]#. IDE controller [primary, secondary] port DMA

acknowledge signal.

Output VDD3

High

DDATA[P,S][15:0]. IO; IDE controller [primary, secondary] port data

bus.

VDD3

3-state 3-state 3-state

DDRQ[P,S]. Input; IDE controller [primary, secondary] port DMA

request signal.

Input-

VDD3

DIOR[P,S]#. Output; IDE controller [primary, secondary] port IO read

command.

Output VDD3

High

DIOW[P,S]#. Output; IDE controller [primary, secondary] port IO write

command.

Output VDD3

High

DRDY[P,S]. Input; IDE controller [primary, secondary] port ready strobe.

Input

VDD3

AMD-766AC Datasheet(PDF) 10 Page - Advanced Micro Devices

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