AMD-766AC datasheet(59/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

C3A41: General Configuration 2 Register

Configuration space; function 3; offset: 41h. Default: 40h.

PMIOEN

TMRRST

PCF9EN

PBIN

TMR32

NO_REBOOT STPGNT

W4SG

W4SG. Wait for stop-grant before deasserting STPCLK#. Read-write. 1=After STPCLK# is asserted for any

reason, it is not deasserted until the corresponding stop-grant cycle is received.

STPGNT. PCI stop-grant cycle specification. Read-write. 0=Stop-grant cycles are detected by the IC as PCI special

cycles in which the address phase AD[4]=1. 1=Stop-grant cycles are detected by the IC as PCI special cycles in

which the data phase AD[31:0]=0012_0002h.

NO_REBOOT. Do not reboot the system when a double TCO timer time out occurs. Read-write. 0=Reboot system

with as specified by PORTCF9[FULLRST] when PM46[2NDTO_STS] is set. 1=Do not reboot the system.

TMR32. ACPI timer size selection. Read-write. 0=The ACPI timer, PM08, is 24 bits. 1=The ACPI timer is 32

bits.

PBIN. Power button in. Read only. This bit reflects the current state of the PWRBTN# pin (before the debounce

circuit). 0=PWRBTN# is asserted.

PCF9EN. Port CF9 enable. Read-write. 1=Enable access to PORTCF9.

TMRRST. ACPI timer reset. Read-write. 1=The ACPI timer, PM08, is held in the asynchronously cleared state.

0=The timer is enabled to count.

PMIOEN. System management IO space enable. Read-write. 1=PMxx, The IO space specified by C3A58, is

enabled.

C3A42: SCI Interrupt Configuration

Configuration space; function 3; offset: 42h. Default: 00h. Read-write.

543:0

Reserved

TRAPSCI

GPIOSCI

SCISEL

SCISEL. SCI interrupt selection. This field specifies the IRQ number routed to the interrupt controllers used for

ACPI-defined SCI interrupts. A value of 0h disables SCI interrupts. Values of 2h, 8h, and Dh are reserved. When

C0A4B[SCI2IOA] is high, the value in this register is ignored and SCI does not enter the PIC. All other values are

valid. See section 4.3.4.1 for details about SCI interrupt routing.

GPIOSCI. General purpose IO SCI enable. 1=Enable SCI/SMI (based on the state of PM04[SCI_EN]) interrupts

when status bits in PMD4 are set while enabled by PMD8. This bit has no affect on whether SMI interrupts are

generated via PM2A[GPIOSMI_EN].

TRAPSCI. Trap SCI enable. 1=Enable SCI/SMI (based on the state of PM04[SCI_EN]) interrupts when status bits

in PMA8 are set while enabled by PMAC. This bit has no affect on whether SMI interrupts are generated via

PM2A[TRPSMI_EN].

C3A43: Power State Register

Configuration space; function 3; offset: 43h.

5:3

2:0

VDDA_STS G3TOS5

PWRFL_STS

PPSTATE

PPSTATE. Previous power state. Read only. This field holds the most previous power state from which the system

entered the FON state. This field resides on the VDD_AUX power plane. This field is encoded as follows:

PPSTATE

Power state

PPSTATE

Power state

Reserved

MOFF mechanical off

POS power on suspend

STR suspend to RAM

STD suspend to disk

SOFF soft off

AMD-766AC Datasheet(PDF) 59 Page - Advanced Micro Devices

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