AMD-766AC datasheet(8/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

3.2

PCI Interface

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

AD[31:0]. Address-data bus.

VDD3

3-state 3-state 3-state

CBE_L[3:0]. Command-byte enable bus.

VDD3

3-state 3-state 3-state

DEVSEL#. Device select.

IO-PU

VDD3

3-state 3-state 3-state

FRAME#. Frame signal.

IO-PU

VDD3

3-state 3-state 3-state

IDSEL. Identification select signal.

Input

VDD3

IRDY#. Master ready signal.

IO-PU

VDD3

3-state 3-state 3-state

PAR. Parity signal.

Output VDD3

3-state 3-state 3-state

PCIRST#. PCI reset. This is the system reset signal for logic that is

Output VDD_

SOFT

Low

High

PCLK. 33 MHz PCI clock. This is required to remain active during reset

and when the IC enters the power-on suspend state (POS).

Input

VDD3

PGNT#. Master grant signal.

Input

VDD3

PIRQ[A, B, C, D]#. PCI interrupt requests. Only PIRQD# is an output

as well as an input; it may be driven active by the USB interrupt. The

other three pins are inputs only.

IOD-

VDD3

PREQ#. Master request signal.

Output VDD3

High

SERR#. PCI system error signal. This may be asserted by the system to

indicate a system error condition. If enabled by RTC70[7], an NMI

interrupt may be generated.

Input-

VDD3

STOP#. Target abort signal.

IO-PU

VDD3

3-state 3-state 3-state

TRDY#. Target ready signal.

IO-PU

VDD3

3-state 3-state 3-state

3.3

Processor Interface

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

A20M#. Address bit[20] mask to the processor. This output is a logical

OR of the KA20G pin from the keyboard controller and PORT92[A20EN].

VDD3

3-state 3-state 3-state

CPURST#. CPURST#. Reset to the processor. This is the reset to

processor(s). See sections 4.1.1 and 4.6.1.5.1.

VDD3

Low

Func.

3-state

FERR#. Floating-point error from the processor. The processor asserts

this signal to indicate a floating-point error has occurred. This is used to

create IRQ13 to the PIC and IOAPIC.

Input

w/H

VDD3

IGNNE#. Ignore numeric error to the processor.

VDD3

3-state 3-state 3-state

INIT#. Initialization interrupt to the processor.

VDD3

3-state 3-state 3-state

INTR. Interrupt request to the processor.

VDD3

Low

low

NMI. Non-maskable interrupt request to the processor.

VDD3

Low

PICCLK. Interrupt message bus clock for the IOAPIC. This is controlled

through C0Ax4B[APICCKS]. During POS, PICCLK may be selected to

either be active or forced low by C3A50[APIC_POSEN].

IOD

VDD3

Func.

PICD0# and PICD1#. Interrupt message bus data bits 1 and 0 for the

IOAPIC.

IOD

VDD3

3-state 3-state 3-state

SMI#. System management interrupt to the processor.

VDD3

3-state 3-state 3-state

STPCLK#. Processor stop-grant request.

VDD3

3-state 3-state

Active

WSC#. Write snoop complete. This signal is used to guarantee the most

recent PCI bus writes from the IC to system memory are visible to the host.

See section 4.3.2 for more details. This signal requires an external pull-up

resistor with a value between 10K to 200K ohms.

IOD

VDD3

3-state 3-state 3-state

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