AMD-766AC datasheet(14/96 Pages) AMD

14 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

3.7

Universal Serial Bus Interface

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

USBCLK. 48 MHz USB clock.

Input

VDD3

USBOC0#. USB over current detect 0. This is expected to become active

to report the occurrence of an over-current condition on the voltage

supplied to the USB ports.

Input

VDD3

USBP[3:0], USBN[3:0]. Analog; USB ports. These are four pairs of

differential USB signals. USBP[3:0] are the positive signals and

USBN[3:0] are the negative signals. These signals go into the high-

impedance state during sleep states; internal logic may detect USB resume

events while in these states and set the status bit, PM20[USB_RSM_STS].

Analog VDD_

USB

3-state 3-state 3-state

3.8

Miscellaneous Signals

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

STRAPH[2:0]. These pins should be tied high through a pull-up resistor

(to VDD_AUX).

Input

VDD_

AUX

---

STRAPL[3:0]. These should be grounded on the system board.

Input

VDD3

TEST#. Scan, NAND tree, and high-impedance mode enable. See

section 9 for details.

Input

VDD3

3.9

Power And Ground

See section 4.6.1.5 for a description of the system power states. The following power and ground planes are

connected to the IC through BGA pins.

VDD3. Main 3.3 volt supply. This plane is required to be valid in the FON and POS power states.

VDD_AUX. Auxiliary 3.3 volt plane. This plane is required to be valid in all system power states except MOFF.

The pins powered by these planes are: PWRBTN#, PWRON#, PME#, SMBUS[C,D], EXTSMI#, SLPBTN#, RI#,

PWRGD, PCIRST#, RPWRON, DCSTOP#, STRAPH[2:0], STRAPL1. All register bits that are on the VDD_AUX

plane are reset by the internal RST_SOFT pulse that is generated for about 30 milliseconds after VDD_AUX

becomes valid.

VDD_REF. 5.0 volt reference supply. This plane is required to be valid in all power states except MOFF. It is

expected that this plane is connected to a 5-volt power supply that is active in the SOFF (soft off) power state, i.e., the

5-volt version of VDD_AUX from the power supply is required for this pin.

VDD_RTC. Real-time clock 3.3 volt supply. This plane is required to be valid in all power states. It is typically

VDD_USB. 3.3 volt supply filtered for the USB transceivers. This plane is required to be valid in all power states

except MOFF.

VSS. Main ground plane.

VSS_USB. Ground plane filtered for the USB transceivers.

AMD-766AC Datasheet(PDF) 14 Page - Advanced Micro Devices

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