AMD-766AC datasheet(3/96 Pages) AMD

3 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

Table of Contents

Overview .................................................................................................................................5

1.1

Features .......................................................................................................................................5

Ordering Information.............................................................................................................6

Signal Descriptions.................................................................................................................7

3.1

Terminology ................................................................................................................................7

3.2

PCI Interface ...............................................................................................................................8

3.3

Processor Interface......................................................................................................................8

3.4

ISA/LPC Bus and Legacy Support Signals.................................................................................9

3.5

Ultra DMA Enhanced IDE Interface ........................................................................................10

3.6

System Management Signals .....................................................................................................11

3.7

Universal Serial Bus Interface...................................................................................................14

3.8

Miscellaneous Signals ................................................................................................................14

3.9

Power And Ground ...................................................................................................................14

Functional Operation ...........................................................................................................15

4.1

Overview ...................................................................................................................................15

4.1.1

Resets............................................................................................................................................... 15

4.2

PCI Interface .............................................................................................................................16

4.2.1

Subtractive Versus Medium Decoding .............................................................................................. 16

4.3

ISA/LPC Bridge And Legacy Logic .........................................................................................16

4.3.1

ISA Bus............................................................................................................................................ 16

4.3.2

LPC Interface ................................................................................................................................... 17

4.3.3

Legacy and Miscellaneous Support Logic ......................................................................................... 17

4.3.4

Interrupt Controllers......................................................................................................................... 18

4.3.4.1

Interrupt Routing Logic ................................................................................................................ 18

4.3.4.2

IOAPIC ........................................................................................................................................ 20

4.3.4.2.1

WSC#..................................................................................................................................... 20

4.3.4.2.2

The IRQ lines ......................................................................................................................... 21

4.3.5

Real-Time Clock (Logic Powered by VDD_AL) ............................................................................... 21

4.4

Enhanced IDE Controller .........................................................................................................21

4.5

USB Controller..........................................................................................................................21

4.5.1

USB Interrupts ................................................................................................................................. 21

4.6

System Management Logic........................................................................................................22

4.6.1

Power Management .......................................................................................................................... 22

4.6.1.1

SCI And SMI Control................................................................................................................... 24

4.6.1.2

Traps............................................................................................................................................ 24

4.6.1.3

System Inactivity Timer................................................................................................................ 25

4.6.1.4

Throttling logic ............................................................................................................................ 25

4.6.1.5

System Power State Controller (SPSC) ......................................................................................... 25

4.6.1.5.1

Transitions Between MOFF/SOFF/STD/STR and FON .......................................................... 27

4.6.1.5.2

Transitions From FON To C2, C3 And POS........................................................................... 28

4.6.1.5.3

Transitions From C2, C3 And POS To FON........................................................................... 28

4.6.2

Serial IRQ Protocol .......................................................................................................................... 29

4.6.3

SMBus Controller ............................................................................................................................ 29

4.6.4

Plug And Play .................................................................................................................................. 30

4.6.5

General Purpose IO .......................................................................................................................... 30

Registers ...............................................................................................................................31

5.1

Register Overview .....................................................................................................................31

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