AD9396SLASHPCB datasheet(29/48 Pages) AD

29 / 48 page

AD9396

Rev. 0 | Page 29 of 48

2-WIRE SERIAL CONTROL REGISTER DETAILS

CHIP IDENTIFICATION

0x00—Bits[7:0] Chip Revision

An 8-bit value that reflects the current chip revision.

PLL DIVIDER CONTROL

0x01—Bits[7:0] PLL Divide Ratio MSBs

The eight most significant bits of the 12-bit PLL divide ratio

PLLDIV.

The PLL derives a pixel clock from the incoming HSYNC

signal. The pixel clock frequency is then divided by an integer

value such that the output is phase locked to HSYNC. This

PLLDIV value determines the number of pixel times (pixels

plus horizontal blanking overhead) per line. This is typically

20% to 30% more than the number of active pixels in the

display.

The 12-bit value of the PLL divider supports divide ratios from

221 to 4095. The higher the value loaded in this register, the

higher the resulting clock frequency with respect to a fixed

HSYNC frequency.

VESA has established some standard timing specifications,

which assists in determining the value for PLLDIV as a function

of horizontal and vertical display resolution and frame rate

(see Table 9).

However, many computer systems do not conform precisely to

the recommendations, and these numbers should be used only

as a guide. The display system manufacturer should provide

automatic or manual means for optimizing PLLDIV. An

incorrectly set PLLDIV usually produces one or more vertical

noise bars on the display. The greater the error, the greater the

number of bars produced.

The power-up default value of PLLDIV is 1693 (PLLDIVM =

0x69, PLLDIVL = 0xDx).

The AD9396 updates the full divide ratio only when the LSBs

are changed. Writing to this register by itself does not trigger an

update.

0x02—Bits[7:4] PLL Divide Ratio LSBs

The four least significant bits of the 12-bit PLL divide ratio

PLLDIV.

The power-up default value of PLLDIV is 1693 (PLLDIVM =

0x69, PLLDIVL = 0xDx).

CLOCK GENERATOR CONTROL

0x03—Bits[7:6] VCO Range Select

Two bits that establish the operating range of the clock

generator. VCORNGE must be set to correspond with the

desired operating frequency (incoming pixel rate). The PLL

gives the best jitter performance at high frequencies. For this

reason, to output low pixel rates and still get good jitter

performance, the PLL actually operates at a higher frequency

but then divides down the clock rate. Table 13 shows the pixel

rates for each VCO range setting. The PLL output divisor is

automatically selected with the VCO range setting.

Table 13. VCO Ranges

VCO Range

Pixel Rate Range

12 to 30

30 to 60

60 to 120

120 to 150

The power-up default value is 01.

Bits[5:3] Charge Pump Current

Three bits that establish the current driving the loop filter in the

clock generator.

Table 14. Charge Pump Currents

Ip2

Ip1

Ip0

Current (μA)

100

150

250

350

500

750

1500

The power-up default value is current = 001.

Bit[2] External Clock Enable

This bit determines the source of the pixel clock.

A Logic 0 enables the internal PLL that generates the pixel clock

from an externally provided HSYNC.

A Logic 1 enables the external CKEXT input pin. In this mode,

the PLL divide ratio (PLLDIV) is ignored. The clock phase

adjusts (phase is still functional). The power-up default value is

EXTCLK = 0.

0x04—Bits[7:3] Phase Adjust

These bits provide a phase adjustment for the DLL to generate

the ADC clock, a 5-bit value that adjusts the sampling phase in

32 steps across one pixel time. Each step represents an 11.25°

shift in sampling phase. The power-up default is 16.

AD9396/PCB Datasheet(PDF) 29 Page - Analog Devices

AD9396/PCB Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Descarga

Enlace URL