AD9396SLASHPCB datasheet(19/48 Pages) AD

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AD9396

Rev. 0 | Page 19 of 48

VSYNC Filter and Odd/Even Fields

The VSYNC filter is used to eliminate spurious VSYNCs,

maintain a consistent timing relationship between the VSYNC

and HSYNC output signals, and generate the odd/even field

output.

The filter works by examining the placement of VSYNC with

respect to HSYNC and, if necessary, slightly shifting it in time at

the VSOUT output. The goal is to keep the VSYNC and

HSYNC leading edges from switching at the same time,

eliminating confusion as to when the first line of a frame

occurs. Enabling the VSYNC filter is done with Register

0x21[5]. Use of the VSYNC filter is recommended for all cases,

including interlaced video and is required when using the

HSYNC per VSYNC counter. Figure 12 illustrates even/odd

field determination in two situations.

FIELD 1

FIELD 0

SYNC SEPARATOR THRESHOLD

FIELD 1

FIELD 0

HSIN

VSIN

VSOUT

O/E FIELD

EVEN FIELD

QUADRANT

Figure 11.

FIELD 1

FIELD 0

SYNC SEPARATOR THRESHOLD

FIELD 1

FIELD 0

HSIN

VSIN

VSOUT

O/E FIELD

ODD FIELD

QUADRANT

Figure 12. VSYNC Filter—Odd/Even

DVI RECEIVER

The DVI receiver section of the AD9396 allows the reception of

a digital video stream compatible with DVI 1.0. Embedded in

this data stream are HSYNCs, VSYNCs and display enable (DE)

signals. DVI restricts the received format to RGB, but the

inclusion of a programmable color space converter (CSC)

allows the output to be tailored to any format necessary. With

this, the scaler following the AD9396 can specify that it always

wishes to receive a particular format—for instance, 4:2:2

YCrCb—regardless of the transmitted mode. If RGB is sent, the

CSC can easily convert that to 4:2:2 YCrCb while relieving the

scaler of this task.

DE GENERATOR

The AD9396 has an on-board generator for DE, for start of

active video (SAV), and for end of active video (EAV), all of

which are necessary for describing the complete data stream for

a BT656-compatible output. In addition to this particular

output, it is possible to generate the DE for cases in which a

scaler is not used. This signal alerts the following circuitry as to

which are displayable video pixels.

4:4:4 TO 4:2:2 FILTER

The AD9396 contains a filter that allows it to convert a signal

from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the

maximum accuracy and fidelity of the original signal.

Input Color Space to Output Color space

The AD9396 can support a wide variety of output formats, such

as the following:

•

RGB 24-bit

•

4:4:4 YCrCb 8-bit

•

4:2:2 YCrCb 8-bit, 10-bit, and 12-bit

•

Dual 4:2:2 YCrCb 8-bit

Color Space Conversion (CSC) Matrix

The color space conversion (CSC) matrix in the AD9396

consists of three identical processing channels. In each channel,

three input values are multiplied by three separate coefficients.

Also included are an offset value for each row of the matrix and

a scaling multiple for all values. Each value has a 13-bit, twos

complement resolution to ensure the signal integrity is main-

tained. The CSC is designed to run at speeds up to 150 MHz

supporting resolutions up to 1080p at 60 Hz. With any-to-any

color space support, formats such as RGB, YUV, YCbCr, and

others are supported by the CSC.

The main inputs, RIN, GIN, and BIN come from the 8-bit to 12-bit

inputs from each channel. These inputs are based on the input

format detailed in Table 11. The mapping of these inputs to the

CSC inputs is shown in Table 10.

Table 10. CSC Port Mapping

Input Channel

CSC Input Channel

R/CR

RIN

Gr/Y

GIN

B/CB

One of the three channels is represented in Figure 13. In each

processing channel the three inputs are multiplied by three

separate coefficients marked a1, a2, and a3. These coefficients

are divided by 4096 to obtain nominal values ranging from

−0.9998 to +0.9998. The variable labeled ‘a4’ is used as an offset

control. The CSC_Mode setting is the same for all three

processing channels. This multiplies all coefficients and offsets

by a factor of 2CSC_Mode.

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