AD9396SLASHPCB datasheet(36/48 Pages) AD

36 / 48 page

AD9396

Rev. 0 | Page 36 of 48

BT656 GENERATION

0x27—Bit[4] BT656 Enable

This bit enables the output to be BT656-compatible with

defined start of active video (SAV) and end of active video

(EAV) controls to be inserted. These require specification of the

number of active lines, active pixels per line, and delays to place

these markers. 0 = disable BT656 video mode. 1 = enable BT656

video mode. The power-up default setting is 0.

0x27—Bit[3] Force DE Generation

This bit allows the use of the internal DE generator in DVI

mode. 0 = internal DE generation disabled. 1 = force DE

generation via programmed registers. The power-up default

setting is 0.

0x27—Bits[2:0] Interlace Offset

These bits define the offset in HSYNCs from Field 0 to Field 1.

The power-up default setting is 000.

0x28—Bits[7:2] VSYNC Delay

These bits set the delay (in lines) from the leading edge of

VSYNC to active video. The power-up default setting is 24.

0x28—Bits[1:0] HSYNC Delay MSBs

These 2 bits along with the following 8 bits set the delay (in

pixels) from the HSYNC leading edge to the start of active

video. The power-up default setting is 0x104.

0x29—Bits[7:0] HSYNC Delay LSBs

See the HSYNC Delay MSBs section.

0x2A—Bits[3:0] Line Width MSBs

These 4 bits along with the following 8 bits set the width of the

active video line (in pixels). The power-up default setting is

0x500.

0x2B—Bits[7:0] Line Width LSBs

See the line width MSBs section.

0x2C—Bits[3:0] Screen Height MSBs

Along with the 8 bits following these 12 bits, set the height of

the active screen (in lines). The power-up default setting is

0x2D0.

0x2D—Bits[7:0] Screen Height LSBs

See the Screen Height MSBs section.

0x2F—Bit[6] TMDS Sync Detect

This read-only bit indicates the presence of a TMDS DE. 0 = no

TMDS DE present. 1 = TMDS DE detected.

0x2F—Bit[5] TMDS Active

This read-only bit indicates the presence of a TMDS clock. 0 =

no TMDS clock present. 1 = TMDS clock detected.

0x2F—Bit[4] AV Mute

This read-only bit indicates the presence of AV mute based on

general control packets. 0 = AV not muted. 1 = AV muted.

0x2F—Bit[3] HDCP Keys Read

This read-only bit reports if the HDCP keys were read

successfully. 0 = failure to read HDCP keys. 1 = HDCP keys

read.

0x2F—Bits[2:0] DV I Quality

These read-only bits indicate a level of DVI quality based on the

DE (display enable) edges. A larger number indicates a higher

quality.

0x30—Bit[5] DVI HSYNC Polarity

This read-only bit indicates the polarity of the DVI HSYNC.

0 = DVI HSYNC polarity is low active. 1 = DVI HSYNC

polarity is high active

0x30—Bit[4] DVI VSYNC Polarity

This read-only bit indicates the polarity of the DVI VSYNC.

0 = DVI VSYNC polarity is low active. 1 = DVI VSYNC polarity

is high active.

MACROVISION

0x31—Bits[7:4] Macrovision Pulse Max

These bits set the pseudo sync pulse width maximum for

Macrovision detection in pixel clocks. This is functional for

13.5 MHz SDTV or 27 MHz progressive scan. Power-up

default is 9.

0x31—Bits[3:0] Macrovision Pulse Min

These bits set the pseudo sync pulse width maximum for

Macrovision detection in pixel clocks. This is functional for

13.5 MHz SDTV or 27 MHz progressive scan. Power-up

default is 6.

0x32—Bit[7] Macrovision Oversample Enable

Tells the Macrovision detection engine whether oversampling

is used. This accommodates 27 MHz sampling for SDTV and

54 MHz sampling for progressive scan and is used as a

correction factor for clock counts. Power-up default is 0.

0x32—Bit[6] Macrovision PAL Enable

Tells the Macrovision detection engine to enter PAL mode when

set to 1. Default is 0 for NTSC mode.

0x32—Bits[5:0] Macrovision Line Count Start

Set the start line for Macrovision detection. Along with Register

0x33, Bits [5:0] they define the region where MV pulses are

expected to occur. The power-up default is Line 13.

0x33—Bit[7] Macrovision Detect Mode

0 = standard definition. 1 = progressive scan mode

AD9396/PCB Datasheet(PDF) 36 Page - Analog Devices

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