AD9396SLASHPCB datasheet(16/48 Pages) AD

16 / 48 page

AD9396

Rev. 0 | Page 16 of 48

Sync Processing

The inputs of the sync processing section of the AD9396 are

combinations of digital HSYNCs and VSYNCs, analog sync-on-

green, or sync-on-Y signals, and an optional external coast

signal. From these signals, it generates a precise, jitter-free (9%

or less at 95 MHz) clock from its PLL; an odd/even field signal;

HSYNC and VSYNC out signals; a count of HSYNCs per

VSYNC; and a programmable SOG output. The main sync

processing blocks are the sync slicer, sync separator, HSYNC

filter, HSYNC regenerator, VSYNC filter, and coast generator.

The sync slicer extracts the sync signal from the green graphics

or luminance video signal that is connected to the SOGIN input

and outputs a digital composite sync. The sync separator’s task

is to extract VSYNC from the composite sync signal, which can

come from either the sync slicer or the HSYNC input. The

HSYNC filter is used to eliminate any extraneous pulses from

the HSYNC or SOGIN inputs, outputting a clean, low jitter

signal that is appropriate for mode detection and clock

generation. The HSYNC regenerator is used to re-create a clean,

although not low jitter, HSYNC signal that can be used for

mode detection and counting HSYNCs per VSYNC. The

VSYNC filter is used to eliminate spurious VSYNCs, maintain a

stable timing relationship between the VSYNC and HSYNC

output signals, and generate the odd/even field output. The

coast generator creates a robust coast signal that allows the PLL

to maintain its frequency in the absence of HSYNC pulses.

AD9396

PLL CLOCK

GENERATOR

HSYNC FILTER

AND

REGENERATOR

HSYNC 0

SOG OUT

HSYNC

COAST

DATACK

SOGIN 0

COAST

CHANNEL

SELECT

VSYNC 1

O/E

FIELD

MUX

RH3

FH4

SP5

MUX

1ACTIVITY DETECT

2POLARITY DETECT

3REGENERATED HSYNC

4FILTERED HSYNC

5SET POLARITY

SP5

AD1

PD2

AD1

PD2

AD1

PD2

SYNC

SLICER

SYNC

SLICER

VSYNC 0

HSYNC 1

HSYNC OUT

VSYNC OUT

SOGIN 1

HSYNC/VSYNC

COUNTER

REG 26H, 27H

SYNC

PROCESSOR

AND

VSYNC FILTER

MUX

PLL SYNC FILTER EN

0x21:6

SP SYNC FILTER EN

0x21:7

SOGOUT SELECT

0x24:2,1

[0x11:7]

HSYNC

SELECT

[0x11:3]

COAST SELECT

0x12:1

VSYNC FILTER EN

0x21:5

FILTER COAST VSYNC

0x12:0

VSYNC

FILTERED

VSYNC

AD1

SP5

MUX

Figure 8. Sync Processing Block Diagram

AD9396/PCB Datasheet(PDF) 16 Page - Analog Devices

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