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AD9551/PCBZ Datasheet(PDF) 7 Page - Analog Devices |
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AD9551/PCBZ Datasheet(HTML) 7 Page - Analog Devices |
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7 / 40 page ![]() AD9551 Rev. B | Page 7 of 40 Parameter Min Typ Max Unit Test Conditions/Comments Input Logic 1 Current 1 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF Output Output Logic 1 Voltage 2.8 V 1 mA load current Output Logic 0 Voltage 0.3 V 1 mA load current SERIAL CONTROL PORT TIMING Table 10. Parameter Limit Unit SCLK Clock Rate, 1/tCLK 50 MHz max Pulse Width High, tHIGH 3 ns min Pulse Width Low, tLOW 3 ns min SDIO to SCLK Setup, tDS 4 ns min SCLK to SDIO Hold, tDH 0 ns min SCLK to Valid SDIO, tDV 13 ns max CS to SCLK Setup (tS) and Hold (tH) 0 ns min CS Minimum Pulse Width High 6.4 ns min |
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