AD9551SLASHPCBZ datasheet(17/40 Pages) AD

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AD9551

Rev. B | Page 17 of 40

DELAY

REFA, REFA

REFB, REFB

REFERENCE

MONITOR

DLL B

DLL A

DELAY

A/B

HOLD A

ACC

A/B

HOLD B

ACC

REF.

DLL

LOCKED

N/2

÷2

DCXO

INPUT

PLL

OUTPUT

PLL

Figure 19. Synchronization Block Diagram

Synchronization/Switchover Control

Figure 19, which is a block diagram of the hitless reference switch-

over circuit, shows that reference synchronization occurs after

the input reference dividers. The synchronization and switchover

functionality relies on the reference monitor logic to control the

operation of the three delay-locked loops (DLLs). The delay blocks

of the three DLLs are identical, so that they exhibit the same time

delay for a given delay value setting.

Note that the DCXO must be operational for the synchroniza-

tion and switchover control to operate.

Both the REFA and REFB paths have a dedicated DLL (DLL A

and DLL B, respectively). DLL A and DLL B are each capable of

operating in either an open-loop or closed-loop mode under the

direction of the reference monitor status signals. When the

reference monitor selects one of the references as the active

reference, the DLL associated with the active reference operates

in open-loop mode. While in open-loop mode, the DLL delays

the active reference by a constant time interval based on a fixed

delay value. As long as one of the references is the active refer-

ence, the other reference is, by default, the alternate reference.

The DLL associated with the alternate reference operates in closed-

loop mode. While in closed-loop mode, the DLL automatically

adjusts its delay so that the rising edge of the delayed alternate

reference is edge-aligned with the rising edge of the delayed

active reference.

When the reference monitor selects one of the references as the

active reference, it switches the output mux to select the output of

the DLL associated with the active reference and, simultaneously,

routes the active reference to the reference DLL. The reference

DLL automatically measures the period of the active reference

(with approximately 250 ps accuracy). When the reference DLL

locks, the value of its delay setting (N) represents one period of

the active reference. Upon acquiring lock, the reference DLL

captures N and divides it by two (N/2 corresponds to a delay value

that represents a half-cycle of the active reference). Both DLL A and

DLL B have access to the N/2 value generated by the reference DLL.

The following paragraphs describe the typical sequence of events

resulting from a device reset, power-up, or return from hold-

over mode.

Active Reference and Alternate Reference

The reference monitor continuously checks for the presence of the

divided REFA and/or REFB signals. If both signals are avail-able,

the device arbitrarily selects one of them as the active reference,

making the other the alternate reference. If only one of the

references is available, it becomes the active reference, making the

other the alternate reference (if it ever becomes available). In

either case, the following two events occur:

•

The output mux selects the output of the active DLL as the

source to the input PLL.

•

The input mux selects the active reference as the source to

the reference DLL.

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