AD9551SLASHPCBZ datasheet(26/40 Pages) AD

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AD9551

Rev. B | Page 26 of 40

SERIAL CONTROL PORT

The AD9551 serial control port is a flexible, synchronous, serial

communications port that allows an easy interface to many

industry-standard microcontrollers and microprocessors. Single

or multiple byte transfers are supported, as well as MSB first or

LSB first transfer formats. The AD9551 serial control port is

configured for a single bidirectional I/O pin (SDIO only).

The serial control port has two types of registers: read-only and

buffered. Read-only registers are nonbuffered and ignore write

commands. All writable registers are buffered (also referred to

as mirrored) and require an I/O update to transfer the new values

from a temporary buffer on the chip to the actual register. To

invoke an I/O update, write a 1 to the I/O update bit found in

changed before issuing an update command, the update simul-

taneously enables all register changes occurring since any

previous update.

SERIAL CONTROL PORT PIN DESCRIPTIONS

SCLK (serial data clock) is the serial shift clock. This pin is an

input. SCLK is used to synchronize serial control port reads and

writes. Write data bits are registered on the rising edge of this

clock, and read data bits are registered on the falling edge. This

pin is internally pulled down by a 30 kΩ resistor to ground.

SDIO (digital serial data input/output) is a dual-purpose pin

that acts as input only or as an input/output. The AD9551

defaults to bidirectional pins for I/O.

CS (chip select bar) is an active low control that gates the read and

write cycles. When CS is high, SDIO is in a high impedance state.

This pin is internally pulled up by a 100 kΩ resistor to 3.3 V and

should not be left floating. See the

section on the use of the

Operation of the Serial Control

Port

CS pin in a communication cycle.

AD9551

SERIAL

CONTROL

PORT

SCLK

SDIO

Figure 24. Serial Control Port

OPERATION OF THE SERIAL CONTROL PORT

Framing a Communication Cycle with CS

The CS line gates the communication cycle (a write or a read oper-

ation). CS must be brought low to initiate a communication cycle.

The CS stall high function is supported in modes where three

or fewer bytes of data (plus instruction data) are transferred.

Bits[W1:W0] must be set to 00, 01, or 10 (see

). In these

modes,

Table 19

CS may temporarily return high on any byte boundary,

allowing time for the system controller to process the next byte. CS

can go high on byte boundaries only and can go high during either

part (instruction or data) of the transfer. During this period, the

serial control port state machine enters a wait state until all data

has been sent. If the system controller decides to abort before

the complete transfer of all the data, the state machine must be reset

either by completing the remaining transfer or by returning the CS

line low for at least one complete SCLK cycle (but fewer than

eight SCLK cycles). A rising edge on the CS pin on a nonbyte

boundary terminates the serial transfer and flushes the buffer.

Table 19. Byte Transfer Count

Bytes to Transfer

(Excluding the 2-Byte Instruction)

Streaming mode

In the streaming mode (Bits[W1:W0] = 11), any number of data

bytes can be transferred in a continuous stream. The register

address is automatically incremented or decremented (see the

MSB/LSB First Transfers section). CS must be raised at the end

of the last byte to be transferred, thereby ending the stream mode.

Communication Cycle—Instruction Plus Data

There are two parts to a communication cycle with the AD9551.

The first part writes a 16-bit instruction word into the AD9551,

coincident with the first 16 SCLK rising edges. The instruction

word provides the AD9551 serial control port with information

regarding the data transfer, which is the second part of the

communication cycle. The instruction word defines whether

the upcoming data transfer is a read or a write, the number of

bytes in the data transfer, and the starting register address for

the first byte of the data transfer.

Write

If the instruction word is for a write operation (Bit I15 = 0), the

second part is the transfer of data into the serial control port

buffer of the AD9551. The length of the transfer (1, 2, or 3 bytes;

or streaming mode) is indicated by two bits (Bits[W1:W0])

in the instruction byte. The length of the transfer indicated by

(Bits[W1:W0]) does not include the 2-byte instruction. CS can

be raised after each sequence of eight bits to stall the bus (except

after the last byte, where it ends the cycle). When the bus is stalled,

the serial transfer resumes when CS is lowered. Stalling on nonbyte

boundaries resets the serial control port.

Read

If the instruction word is for a read operation (Bit I15 = 1), the

next N × 8 SCLK cycles clock out the data from the address

specified in the instruction word, where N is 1, 2, 3, or 4, as

determined by Bits[W1:W0]. In this case, 4 is used for streaming

mode, where four or more words are transferred per read. The

data read back is valid on the falling edge of SCLK.

The default mode of the AD9551 serial control port is bidirec-

tional mode, and the data read back appears on the SDIO pin.

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