AD9551SLASHPCBZ datasheet(22/40 Pages) AD

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AD9551

Rev. B | Page 22 of 40

The value of K depends on the device configuration, as shown

in Table 16.

Table 16. Configuring the Value of K

Mode

fCRYSTAL

Description

19.44 MHz

52 MHz

1300/243

Using 2× multiplier

325/243

Using 2× divider

50 MHz

1250/243

Using 2× multiplier

625/486

Using 2× divider

49.86 MHz

277/54

Using 2× multiplier

277/216

Using 2× divider

49.152 MHz

2048/405

Using 2× multiplier

512/405

Using 2× divider

Normal

Crystal independent

The user must carefully consider the operating frequency of the

externally connected crystal resonator (assuming that the input

PLL is not bypassed). Because the DCXO is capable of pulling

the crystal over a 50 ppm range only, the output frequency of

the DCXO is essentially identical to the crystal frequency.

The denominator of Equation 1 is the input division factor, which

has an integer part (Nx) due to an integer divider, as well as an

optional fractional part that is associated with the input SDM.

1/2 + FRACx/(2 × MODx)

Note that when bypassing the SDM, the device forces the frac-

tional part to 0 (equivalent to FRACx = −MODx).

The numerator of Equation 2 contains the feedback division

factor, which has an integer part (N) due to an integer divider,

as well as an optional fractional part (FRAC/MOD) that is

associated with the feedback SDM.

Equation 1 and Equation 2, along with the constraints placed on

their variables, imply a rational relationship between fREF and fOUT1.

That is, the ratio fOUT1/fREF must be expressible as a ratio of two

integers. For example, it is not possible to configure the device

to satisfy a frequency ratio having a value of −2 because it is

irrational (that is, not expressible as a ratio of two integers).

CALCULATING DIVIDER VALUES

This section provides a 5-step procedure for calculating the divider

values when given a specific fOUT1/fREF ratio. The methodology is

described in general terms, but a specific example is provided

for clarity. The example assumes the use of the frequency control

pins with A[3:0] = 0010 and Y[3:0] = 0100 (see Table 13 and

Table 14). The example parameters are as follows:

MHz

239

622

⎟

⎞

⎜

237 ⎠

⎛

⎝

REF

MHz

625

⎟

⎠

⎞

⎜

⎝

OUT1

MHz

⎛

Calculation Steps

Ensure that fOUT1 and fREF are rationally related.

As shown in the following equation, fOUT1/fREF is expressible

as a ratio of two integers, so fOUT1 and fREF are rationally related.

568

553

951

977

)

)(

239

(

62208

)

100

)(

237

)(

(

625

237

239

622

625

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

REF

OUT1

000

625

Determine the output divide factor (ODF).

Note that the VCO frequency (fVCO) spans 3350 MHz to

4050 MHz. The ratio, fVCO/fOUT1, indicates the required ODF.

Given the specified value of fOUT1 (~644.53 MHz) and the

range of fVCO, the ODF spans a range of 5.2 to 6.3. The ODF

must be an integer, which means that ODF = 6 (because 6

is the only integer between 5.2 and 6.3).

Determine suitable values for P0 and P1.

The ODF is the product of the two output dividers; that is,

ODF = P0 × P1. It has already been determined that ODF = 6

for the given example. Therefore, we have P0 × P1 = 6, with the

constraints that P0 and P1 are both integers and that 4 ≤ P0 ≤ 11

(see the Output/Input Frequency Relationship section).

These constraints lead to the singular solution of P0 = 6, and P1

= 1.

Although this particular example yields a singular solution

for the output divider values with fOUT1 ≈ 644.53 MHz, some

fOUT1 frequencies result in multiple ODFs rather than just

one. For example, if fOUT1 = 100 MHz, the ODF ranges from

34 to 40. This leads to an assortment of possible values for

P0 and P1, as shown in Table 17.

The P0 and P1 combinations listed in Table 17 are all equally

valid. However, note that they yield only three valid ODF

values (35, 36, and 40) from the original range of 34 to 40.

Table 17. Combinations of P0 and P1

ODF

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