AD9551SLASHPCBZ datasheet(14/40 Pages) AD

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AD9551

Rev. B | Page 14 of 40

PRESET FREQUENCY RATIOS

The frequency selection pins (A[3:0], B[3:0], and Y[3:0]) allow

the user to hardwire the device for preset input and output divider

values based on the pin logic states. The A[3:0] pins control the

REFA dividers, the B[3:0] pins control the REFB dividers, and

the Y[3:0] pins control the feedback and output dividers. The

pins decode ground or open connections as Logic 0 or Logic 1,

respectively. To override the preset divider settings, use the serial

I/O port to program the desired divider values.

Table 13 lists the input divider values based on the logic state of

the frequency selection pins. The table headings are as follows:

•

A[3:0], B[3:0]. The logic state of the A[3:0] or B[3:0] pins.

•

NA, NB. The integer part of the REFA input divider (NA) or

the REFB input divider (NB).

•

MODA, MODB. The modulus of the REFA input divider

SDM (MODA) or the REFB input divider SDM (MODB).

•

FRACA, FRACB. The fractional part of the REFA input

divider SDM (FRACA) or the REFB input divider SDM

(FRACB).

•

fREFA, fREFB. The frequency of the REFA input (fREFA) or the

REFB input (fREFB).

The divider settings shown in Table 13 cause the frequency at the

reference input of the output PLL’s PFD (fIF) to operate at exactly

26 MHz when using the indicated input reference frequency,

fREFA or fREFB, assuming the use of a 26 MHz external crystal.

Table 13. Preset Input Settings

A[3:0], B[3:0]

NA, NB

MODA, MODB

FRACA, FRACB

fREFA, fREFB (MHz)1

0000

130,000

110,800

622.08

0001

130,000

−120,000

625

0010

154,050

−114,594

( )

627

622

237

239

≈

0011

130,000

45,200

()

641

622

≡

0100

166,400

96,400

()

53125

644

625

≡

0101

104,000

−44,625

421875

657

10518

≡

0110

198,016

−42,891

()

660

238

239

10518

≈

0111

154,700

41,820

()

666

622

238

255

≈

1000

154,050

74,970

()

669

622

237

255

≈

1001

182,000

93,000

()

669

625

≈

1010

153,400

108,120

()

255

672

622

236

≈

1011

197,184

67,998

() ( )

255

693

625

237

≈

1100

146,900

83,612

()

253

696

622

226 ≈

1101

198,016

−161,755

()

255

10518

704

238

≈

1110

197,184

−115,995

()

255

10518

707

237

≈

11112

19.44 MHz mode

1 Assumes the use of a 26 MHz external crystal.

2 If all four A[3:0] pins or all four B[3:0] pins are Logic 1, the 19.44 MHz mode is in effect.

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