MPC8377ECVRAFDA datasheet(36/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Local Bus

Table 38 describes the general timing parameters of the local bus interface of the device.

Figure 19 provides the AC test load for the local bus.

Figure 19. Local Bus AC Test Load

Table 39. Local Bus General Timing Parameters—PLL Bypass Mode

Parameter

Symbol1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Input setup to local bus clock

tLBIVKH

7.0

—

3, 4

Input hold from local bus clock

tLBIXKH

1.0

—

3, 4

LALE output fall to LAD output transition (LATCH

hold time)

tLBOTOT1

1.5

—

LALE output fall to LAD output transition (LATCH

hold time)

tLBOTOT2

3.0

—

LALE output fall to LAD output transition (LATCH

hold time)

tLBOTOT3

2.5

—

Local bus clock to output valid

tLBKHOV

—3.0

Local bus clock to output high impedance for

LAD/LDP

tLBKHOZ

—

4.0

3, 8

Note:

1 The symbols used for timing specifications herein follow the pattern of t

(First two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case

for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect

to the output (O) going invalid (X) or output hold time.

2 All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3 All signals are measured from LBV

DD/2 of the rising/falling edge of LCLK0 to 0.4 × LBVDD of the signal in question for 3.3-V

signaling levels.

4 Input timings are measured at the pin.

5 t

LBOTOT1 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on

LAD output pins.

6 t

LBOTOT2 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD

output pins.

7 t

LBOTOT3 should be used when LBCR[AHD] is set and the load on LALE output pin equals to the load on LAD output pins.

8 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

MPC8377ECVRAFDA Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc

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