| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
MPC8377ECVRAFDA Datasheet(PDF) 78 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8377ECVRAFDA Datasheet(HTML) 78 Page - Freescale Semiconductor, Inc |
|
78 / 124 page ![]() MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 78 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Figure 51. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mVp-p. 21.2 SerDes Reference Clocks The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of SerDes2. The following sections describe the SerDes reference clock requirements and some application information. 21.2.1 SerDes Reference Clock Receiver Characteristics Figure 52 shows a receiver reference diagram of the SerDes reference clocks. • SerDes Reference Clock Receiver Reference Circuit Structure —The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 52. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50 Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. Differential Swing, VID or VOD = A – B A Volts B Volts SD n_TX or SD n_RX SD n_TX or SD n_RX Differential Peak Voltage, VDIFFp = |A – B| Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown) Vcm = (A + B)/2 |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |