MPC8377ECVRAFDA datasheet(59/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

PCI Express

15.2

AC Requirements for PCI Express SerDes Clocks

Table 50 lists the PCI Express SerDes clock AC requirements.

15.3

Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

15.4

Physical Layer Specifications

Following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer please use the PCI Express

Base Specification, Rev. 1.0a.

NOTE

The voltage levels of the transmitter and the receiver depend on the SerDes

control registers which should be programmed at the recommended values

for PCI Express protocol (that is, L1_nVDD = 1.0 V).

Table 50. SD_REF_CLK and SD_REF_CLK AC Requirements

Parameter

Symbol

Min

Typical

Max

Unit

Notes

REFCLK cycle time

tREF

—10

—

REFCLK cycle-to-cycle jitter. Difference in the period of any

two adjacent REFCLK cycles.

tREFCJ

—

100

—

REFCLK phase jitter peak-to-peak. Deviation in edge

location with respect to mean edge location.

tREFPJ

–50

—

+50

—

SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)

tCKCJ

—

100

—

SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in

edge location with respect to mean edge location.

tCKPJ

–50

—

+50

2, 3

Note:

1 All options provide serial interface bit rate of 1.5 and 3.0 Gbps.

2 In a frequency band from 150 kHz to 15 MHz, at BER of 10-12.

3 Total peak-to-peak Deterministic Jitter “J

D” should be less than or equal to 50 ps.

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