MPC8377ECVRAFDA datasheet(62/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

PCI Express

15.4.2

Transmitter Compliance Eye Diagrams

The Tx eye diagram in Figure 42 is specified using the passive compliance/test measurement load (see

Figure 44) in place of any real PCI Express interconnect + Rx component. There are two eye diagrams that

must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate the

center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a

Common mode return

loss

Measured over 50 MHz to

1.25 GHz.

RLTX-CM

6—

—

DC differential Tx

impedance

Tx DC differential mode low

impedance

ZTX-DIFF-DC

100

120

—

Transmitter DC

impedance

Required Tx D+ as well as D–

DC impedance during all

states

ZTX-DC

—

Lane-to-Lane output

skew

Static skew between any two

transmitter lanes within a

single link

LTX-SKEW

—

500 +

2UI

—

AC coupling capacitor

All transmitters should be AC

coupled. The AC coupling is

required either within the

media or within the

transmitting component itself.

CTX

—

200

—

Crosslink random

timeout

This random timeout helps

resolve conflicts in crosslink

configuration by eventually

resulting in only one

downstream and one

upstream port.

Tcrosslink

0—

Note:

1 No test load is necessarily associated with this value.

2 Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 44 and measured over

any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 42.)

3 A T

TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the

transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total

Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.

The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed

to the averaged time value.

4 The transmitter input impedance will result in a differential return loss greater than or equal to 12 dB and a common mode

return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement

applies to all valid input levels. The reference impedance for return loss measurements is 50

Ω to ground for both the D+ and

D– line (that is, as measured by a vector network analyzer with 50-

Ω probes, see Figure 44). Note that the series capacitors,

CTX, is optional for the return loss measurement.

5 Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 44 for both V

TX-D+ and VTX-D-.

6 See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.

7 See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.

Table 51. Differential Transmitter (Tx) Output Specifications (continued)

Parameter

Conditions

Symbol

Min

Typical

Max

Units

Notes

MPC8377ECVRAFDA Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc

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