MPC8535EBVTATH datasheet(33/126 Pages) FREESCALE

33 / 126 page

DDR2 and DDR3 SDRAM

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Figure 8 shows the DDR2 and DDR3 SDRAM interface input timing diagram.

Figure 8. DDR SDRAM Input Timing Diagram

Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface

At recommended operating conditions with GVDD of 1.5 V ± 5%. DDR3 data rate is between 606MHz and 667MHz.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.175

—

AC input high voltage

VIH

MVREF + 0.175

—

Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications

At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC

tCISKEW

—

1, 2

667 MHz

—

–240

240

—

533 MHz

—

–300

300

—

400 MHz

—

–365

365

—

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will

be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined

by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value

of tCISKEW.

3. Maximum DDR2 and DDR3 frequency is 667MHz.

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

MPC8535EBVTATH Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc

MPC8535EBVTATH Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL