MPC8535EBVTATH datasheet(41/126 Pages) FREESCALE

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

2.9.2

FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.

2.9.2.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI specifications, since

they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO

interface provides deliberate skew between the transmitted data and source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface.

That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin

TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed

copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for

example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-

synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the

eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and

the platform speed. For more information see Section 2.4.6, “Platform to FIFO Restrictions.”

A summary of the FIFO AC specifications appears in Table 26 and Table 27.

Table 25. RGMII, RTBI, and FIFO DC Electrical Characteristics

Parameters

Symbol

Min

Max

Unit

Notes

Supply voltage 2.5 V

LVDD/TVDD

2.37

2.63

1,2

1 LV

DD supports eTSECs 1.

2 TV

DD supports eTSECs 3.

Output high voltage

(LVDD/TVDD = Min, IOH = –1.0 mA)

VOH

2.00

LVDD/TVDD + 0.3

—

Output low voltage

(LVDD/TVDD = Min, IOL = 1.0 mA)

VOL

GND – 0.3

0.40

—

Input high voltage

VIH

1.70

LVDD/TVDD + 0.3

—

Input low voltage

VIL

–0.3

0.70

—

Input high current

(VIN = LVDD, VIN = TVDD)

IIH

—10

μA

1, 2,3

3 Note that the symbol V

IN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.

Input low current

(VIN = GND)

IIL

–15

—

μA

Note:

Table 26. FIFO Mode Transmit AC Timing Specification

Parameter/Condition

Symbol

Min

Typ

Max

Unit

TX_CLK, GTX_CLK clock period2

tFIT

6.0

8.0

100

TX_CLK, GTX_CLK duty cycle

tFITH

TX_CLK, GTX_CLK peak-to-peak jitter

tFITJ

—

250

MPC8535EBVTATH Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc

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