MPC8535EBVTATH datasheet(53/126 Pages) FREESCALE

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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Figure 27 provides the AC test load for eTSEC.

Figure 27. eTSEC AC Test Load

Figure 28 shows the RMII receive AC timing diagram.

Figure 28. RMII Receive AC Timing Diagram

2.9.3

SGMII Interface Electrical Characteristics

Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of MPC8535E as shown in

Figure 29, where CTX is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential

pair features 50-

Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to

S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 68.

When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be

left floating. The input signals should be terminated based on the guidelines described in Section 3.6, “Connection

Recommendations,” as long as such termination does not violate the desired POR configuration requirement on these pins, if

applicable.

Fall time TSECn_RX_CLK (80%–20%)

tRMRF

1.0

—

2.0

RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge

tRMRDV

4.0

——ns

RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge

tRMRDX

2.0

——ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going

to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For example, the

subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

Table 37. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

TSECn_RX_CLK

RXD[1:0]

tRMRDX

tRMR

tRMRH

tRMRR

tRMRF

CRS_DV

RX_ER

tRMRDV

Valid Data

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