MPC8535EBVTATH datasheet(99/126 Pages) FREESCALE

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PCI Express

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

2.21

PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8535E.

2.21.1

DC Requirements for PCI Express SD1_REF_CLK and

SD1_REF_CLK

For more information, see Section 2.20.2, “SerDes Reference Clocks.”

2.21.2

AC Requirements for PCI Express SerDes Clocks

Table 70 lists AC requirements.

2.21.3

Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all

times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.

2.21.4

Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well

as the specifications of the transport and data link layer, please use the PCI Express Base Specification. REV. 1.0a document.

2.21.4.1

Differential Transmitter (TX) Output

Table 71 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the

component pins.

Table 70. SD1_REF_CLK and SD1_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Notes

tREF

REFCLK cycle time

—

tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

——

100

—

tREFPJ Phase jitter. Deviation in edge location with respect to mean edge

location

–50

—

1,2,3

Notes:

1. Tj at BER of 10E-6 86 ps Max.

2. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 42 ps.

3. Limits from “PCI Express CEM Rev 2.0” and measured per “PCI Express Rj, D, and Bit Error Rates”.

Table 71. Differential Transmitter (TX) Output Specifications

Symbol

Parameter

Min

Nom

Max

Units

Comments

Unit Interval

399.88

400

400.12

Each UI is 400 ps ± 300 ppm. UI does not account for

Spread Spectrum Clock dictated variations. See Note

VTX-DIFFp-p

Differential

Peak-to-Peak

Output Voltage

0.8

—

1.2

VTX-DIFFp-p = 2*|VTX-D+ – VTX-D-| See Note 2.

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