MPC8535EBVTATH datasheet(60/126 Pages) FREESCALE

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MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Ethernet Management Interface Electrical Characteristics

Freescale Semiconductor

The IEEE 1588 AC timing specifications are in Table 43.

2.10

Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals EC_MDIO (management data

input/output) and EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and

RTBI are specified in Section 2.9, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management”

Table 43. eTSEC IEEE 1588 AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Note

TSEC_1588_CLK clock period

tT1588CLK

3.8

—

TTX_CLK*7

TSEC_1588_CLK duty cycle

tT1588CLKH

/tT1588CLK

—

TSEC_1588_CLK peak-to-peak jitter

tT1588CLKINJ

——

250

—

Rise time eTSEC_1588_CLK (20%–80%)

tT1588CLKINR

1.0

—

2.0

—

Fall time eTSEC_1588_CLK (80%–20%)

tT1588CLKINF

1.0

—

2.0

—

TSEC_1588_CLK_OUT clock period

tT1588CLKOUT

2*tT1588CLK

——ns

—

TSEC_1588_CLK_OUT duty cycle

tT1588CLKOTH

/tT1588CLKOUT

—

TSEC_1588_PULSE_OUT

tT1588OV

0.5

—

3.0

—

TSEC_1588_TRIG_IN pulse width

tT1588TRIGH

2*tT1588CLK_MAX

——

Note:

1. When TMR_CTRL[CKSEL]=00, the external TSEC_1588_CLK input is selected as the 1588 timer reference clock source,

with the timing defined in the Table above. The maximum value of tT1588CLK is defined in terms of TTX_CLK, which is the

maximum clock cycle period of the equivalent interface speed that the eTSEC1 port is running

When eTSEC1 is configured to operate in the parallel mode, the TTX_CLK is the maximum clock period of the

TSEC1_TX_CLK. When eTSEC1 operates in SGMII mode, the maximum value of tT1588CLK is defined in terms of the

recovered clock from SGMII SerDes. For example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be

2800, 280, and 56 ns respectively.

See the

MPC8536E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description of

TMR_CTRL registers.

2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the

MPC8536E

PowerQUICC™ III Integrated Processor Reference Manual for a description of TMR_CTRL registers.

MPC8535EBVTATH Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc

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