L4969UR-E datasheet(31/46 Pages) STMICROELECTRONICS

31 / 46 page

L4969UR-E, L4969URD-E

Control and status registers

Doc ID 022587 Rev 2

31/46

After the XTAL driven timer of the microcontroller has calculated the relative cycle time and

the corresponding deviation, CG1 and CG0 have to be set to ‘10’ to disable the adjustment

cycle on NINT. From the deviation calculated by the microcontroller, the correction factor of

the RC-oscillator -15% to 16% can be reprogrammed with CG1 and CG0 set to ‘00’ or ‘11’.

(‘11’ can be used to indicate that calibration has already been performed).

Note, that overwriting this register is only valid, if the cycle measurement was started and

terminated properly. This can be tested by evaluating PGEN either prior to or during

correction (Read back via SOUT).

Note also, that any write to the WDC register will reset the timer and thus reset the phase of

the testcycle. Therefore a cyclic access to the window watchdog during the pulsewidth

measurement has to be avoided and the timer watchdog to be used instead (i.e. 1 sec)

Figure 16.

State transition during oscillator calibration

4.5

ADR4: WDC watchdog control register

Figure 17.

ADR4: WDC watchdog control register

The startup watchdog is not programmable and will always generate a 1.0 ms low cycle on

NRESET followed by a 320 ms high cycle until an Acknowledgment will occur. If no

Acknowldege is received after the 7th cycle, the device will automatically be forced into

Sleep mode.

“No Request”

“2.5ms cycle

on NINT”

“Finish Cycle”

“Update ADJ”

CG=01

CG=10

CG=00

CG=11

Watchdog and Interrupt

Start time measurement

at rising edge

Calculate

Offset

Write offset

Watchdog and Interrupt can be enabled

has to be disabled

SWT0

WDT3

SWT1

WND

WDEN

WDT2

WDT1

WDT0

Wake-up Watchdog

timing configuration

0000: 80ms

0001: 160ms

0010: 320ms

0011: 640ms

0100: 800ms

1000: 1sec

1001: 2sec

1010: 4sec

1011: 8sec

1100: 45min

Software Window Watchdog

timing configuration

00: 2.5 - 5ms

01: 5 - 10ms

10: 10 - 20ms

11: 20 - 40ms

Enable Wakeup Watchdog,

Window Watchdog will be

automatically deactivated

until wakeup watchdog expires

Reserved bits (‘RES’) have to be written as ‘0’.

Disable

Window Watchdog,

only allowed with

PGEN set, see

previous table

for Osc adjust

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