RM0319 datasheet(115/368 Pages) STMICROELECTRONICS

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RM0319

USB 2.0 Host ports (UHC)

Doc ID 022640 Rev 3

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clock from either high-speed data or low-speed data indicated by SIE_Switch HCLK input

from SIETx State Machine.

HSIE functionality

The functionality of the Host Serial Interface Engine (HSIE) is to receive and transmit the

USB data over D+ and D- lines in accordance with the USB protocol. During the reception of

USB data, the D+ and D- signals are passed through the differential receiver (which is

external to the UHOSTC controller) to get a single ended bit stream that is passed through

the PLL Block to extract the clock and data information. The Clock and data are passed to

the SIE Block to identify the Sync Pattern and for NRZI-NRZ conversion. This NRZ data is

then passed through the Bit Stripper which strips off the excessive zeros inserted, The data

stream is initially passed through the PID Decode and checker to identify different PIDs.

Depending upon the type of PID, the HSIE block handles the protocol accordingly.

RootHub port configuration

The port configuration block implements part of the RootHub logic. This block is separated

from the main RootHub block to distinguish the logic that varies with design requirements. In

short, this block implements part of the OHCI registers that are specific to RootHub and a

state machine for every DownStreamPort to control the port functional states.

This block has the following submodules:

●

RootHub port registers

●

Port S/M

●

Port receive

●

Port resume

●

Port MUX

10.4

Interrupts

EHCI block generates one interrupt when the following conditions are occurred:

●

Interrupt on Async Address

●

Host System Error

●

Frame List Rollover

●

Port Change

●

USB Error

●

USB Interrupt

This interrupt is generated only when the corresponding bits of USBINTR register are

enabled. This interrupt is connected to IRQ26 of the CPU (Table 125: Interrupt requests).

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