RM0319 datasheet(112/368 Pages) STMICROELECTRONICS

112 / 368 page

USB 2.0 Host ports (UHC)

RM0319

112/368

Doc ID 022640 Rev 3

List processor

The List Processor is the main block of the EHCI Host Controller. The List Processor is

implemented with multiple state machines to perform the list service flow, which is set up by

the Host Controller Driver (HCD) according to the priority set in the Operational registers

Section : Operational registers

In addition, the List Processor consists of a controller that interfaces with all the other EHCI

Host Controller blocks, such as the AHB BIU (Master module), the Packet Buffer, the EHCI

Operational registers, the SOF Generators and the Root Hub.

Operational registers

This block exposes the implemented EHCI Capability and Operational registers as defined

in the USB EHCI specification. In addition, certain IP-specific extended registers are also

implemented, in order to configure features like Packet Buffer depth, break memory transfer,

frame length.

The Operational registers block interfaces with the AHB BIU (Slave module), the List

Processor and the Root Hub.

Start-Of-Frame (SOF) generator

The SOF Generator block implements the counter which generates the Start-Of-Frame

(SOF) packets to supply micro-SOFs for each microframe. The SOF counter runs in the

PHY clock domain.

Microframe duration is derived from the EHCI Frame Length Adjustment (FLADJ) register

value. This ensures that the Host microframe duration and per-port microframe duration

remain the same.

This block interfaces with the List Processor only.

Packet buffer

The Packet Buffer (PBUF) block provides storage and control for IN/OUT data transaction,

with a configured size of 1024 bytes (256 x 32 = 1024 bytes).

According to its functionality, the PBUF block interface with both the List Processor and the

Root Hub. Specifically, during an OUT transaction, the List Processor fetches data from the

system memory and writes them in the PBUF. Besides, during an IN transaction, the data

are written to PBUF by the Root Hub Section : Root hub.

The Packet Buffer size depends on the system latency and bandwidth allocated to the EHCI

Host Controller. For example, in case PBUF size is programmed to 64 bytes, a 1024-bytes

IN transfer would get 1024/64 = 16 data transfer on the AHB bus. If the system is not able to

ensure EHCI access to AHB bus for these 16 transfers with no breaks, then a buffer overrun

occurs. In this case, to avoid buffer overrun or under-run, PBUF size could be set to 1024

bytes.

Root hub

The Root Hub (RH) block interfaces between the List Processor and the USB PHY. It

propagates reset and resume signals to downstream ports, and handles port connections

and disconnections.

The RH operates both on the local PHY clock (a free-running 30/60 MHz clock) and on the

clock source from each physical port (30 MHz with a 16 bit interface).

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