AS1163 datasheet(45/91 Pages) AMSOSRAM

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AS1163

Functional description

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Note: The I²C master in the AS1163 has one known behavior: In a read transaction the last

pulse (clock and data) for final NACK is not emitted. Most I²C devices will sync on the

subsequent STOP condition, so the read terminates successfully, however, there might be

devices that go out of sync. I²C clock stretching is not supported.

When channel 2 is configured as I²C bridge, the current level of the driver can still be

configured via SETCURCHN.

A value of 3mA (CUR=1) is recommended as the minimum current requirement for the lower

bound of an external pull up resistor, 2.2 kOhm, is 2.5 mA.

6.8.2

I²C control register

I²C control register is an 8-bit register that contains the division factor to set the I²C speed.

Default value at startup is 0xC (1100 or 12 dec). The complete division factor must be left

shifted by 3 bits, so that the real division factor is 1100000 (96 dec). This value is used to

divide the sys clock to generate the I²C half clock period. With a main clock of 19.2 MHz this

means an I²C frequency of about 92 kHz.

The formular to calculate the target I²C frequency from the register setting is the following,

assuming nominal I²C loading conditions given by 5 kOhm pull-up resistor and 20 pF parasitic

line capacitance (division factor can be subject of minor deviations depending on the bus

loading conditions as an effect of the I²C master sensing the line to ensure the bus is idle upon

starting transmission):

Equation 3:

�� = ��/(2 ∗ (8 ∗ ��2��_�� + 7))

Note: Typically, f_SCL=1371kHz at I2C_SPEED=0; f_SCL=417 kHz at I2C_SPEED=2.

Information:

Divisor must be different from 0, so writing it to 0 must be avoided.

AS1163 Datasheet(PDF) 45 Page - ams-OSRAM AG