AS1163 datasheet(46/91 Pages) AMSOSRAM

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AS1163

Functional description

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Table 13: I²C control register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3:0

I2C_INT

I2C_12BITADDR

I2C_NACKACK

I2C_BUSY

I2C_SPEED

Read

Read/write

Read

Read/write

High when

INT pad (B2)

is connected

to GND

Sets 12-bit addressing

mode for I2CREAD

and I2CWRITE

telegrams

Status of ack bit of last

I²C transaction

Set if the last

I²C transaction

was completed

Division factor to set the

speed of the I²C bus

(see formula above)

Within the I2CCFG register only bit 3:0 plus bit 6 can be written, the other bits are read only.

The I2CCFG register allows to check the actual division factor for I²C speed. It is also

recommended to read this register after every I²C operation and check the bit 5 with nack/ack

information: When this is 1, it means that last I²C read or write operation ended with a NACK

from the I²C device so an error occurred, if this bit is 0 the last communication ended correctly

with an ACK.

If bit 4 is still 1, it means that the I²C device is still busy and the last read or write operation is

not finished yet.

Setting bit 6 of I²C control register will enable the use of devices that require 12-bit addressing

via I²C.

Bit 7 will be set if the I²C interrupt pin is low; there is no latching.

6.9

SYNC configuration

When the SYNC_EN bit is set in the CURRENT register, new PWM values are not applied

until a sync signal is received. The sync can be either software, given form the SYNC

command, or hardware, from a toggling of the sync pin. In this last case, also the

SYNC_PIN_EN bit must be set in the OTP.

This functionality is required for display-like applications.

6.9.1

SYNC pin activation

The SYNC pin functionality is activated by a dedicated OTP bit SYNC_PIN_EN (see Table 6).

If the OTP bit is not set, the SYNC telegram can be used instead.

AS1163 Datasheet(PDF) 46 Page - ams-OSRAM AG

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