ADT7463ARQZ-R7 datasheet(12/52 Pages) ONSEMI

12 / 52 page

REV. C

–12–

ADT7463

ADT7463 WRITE OPERATIONS

The SMBus specification defines several protocols for different

types of read and write operations. The ones used in the ADT7463

are discussed below. The following abbreviations are used in the

diagrams:

S – START

P– STOP

R– READ

W – WRITE

A– ACKNOWLEDGE

A – NO ACKNOWLEDGE

The ADT7463 uses the following SMBus write protocols.

Send Byte

In this operation, the master device sends a single command

byte to a slave device as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA and the

transaction ends.

For the ADT7463, the send byte protocol is used to write a

the same address. This is illustrated in Figure 10.

SLAVE

ADDRESS

A P

ADDRESS

Figure 10. Setting a Register Address for Subsequent Read

If it is required to read data from the register immediately after

setting up the address, the master can assert a repeat start con-

dition immediately after the final ACK and carry out a single

byte read without asserting an intermediate stop condition.

Write Byte

In this operation, the master device sends a command byte and

one data byte to the slave device as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

7. The slave asserts ACK on SDA.

8. The master asserts a stop condition on SDA to end the

transaction.

This is illustrated in Figure 11.

SLAVE

ADDRESS

A DATA AP

ADDRESS

Figure 11. Single Byte Write to a Register

ADT7463 READ OPERATIONS

The ADT7463 uses the following SMBus read protocols.

Receive Byte

This is useful when repeatedly reading a single register. The

operation, the master device receives a single byte from a slave

device as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts ACK on SDA.

4. The master receives a data byte.

5. The master asserts NO ACK on SDA.

6. The master asserts a stop condition on SDA and the trans-

action ends.

In the ADT7463, the receive byte protocol is used to read a

single byte of data from a register whose address has previously

been set by a send byte or write byte operation.

SLAVE

ADDRESS

RA DATA A P

Figure 12. Single Byte Read from a Register

ALERT RESPONSE ADDRESS

Alert response address (ARA) is a feature of SMBus devices that

allows an interrupting device to identify itself to the host when

multiple devices exist on the same bus.

The SMBALERT output can be used as an interrupt output or

can be used as an SMBALERT. One or more outputs can be

connected to a common SMBALERT line connected to the

master. If a device’s SMBALERT line goes low, the following

procedure occurs:

1. SMBALERT is pulled low.

2. Master initiates a read operation and sends the alert response

address (ARA = 0001 100). This is a general call address

that must not be used as a specific device address.

3. The device whose SMBALERT output is low responds to

the alert response address, and the master reads its device

address. The address of the device is now known and it can

be interrogated in the usual way.

4. If more than one device’s SMBALERT output is low, the one

with the lowest device address will have priority in accordance

with normal SMBus arbitration.

5. Once the ADT7463 has responded to the alert response

address, the master must read the status registers and the

SMBALERT will only be cleared if the error condition has

gone away.

SMBUS TIMEOUT

The ADT7463 includes an SMBus timeout feature. If there is

no SMBus activity for 35 ms, the ADT7463 assumes that the bus

is locked and releases the bus. This prevents the device from

locking or holding the SMBus expecting data. Some SMBus

controllers cannot handle the SMBus timeout feature, so it

can be disabled.

CONFIGURATION REGISTER 1 – Register 0x40

<6> TODIS = 0; SMBus Timeout ENABLED (Default)

<6> TODIS = 1; SMBus Timeout DISABLED

Rev. 4 | Page 12 of 52 | www.onsemi.com

ADT7463ARQZ-R7 Datasheet(PDF) 12 Page - ON Semiconductor

ADT7463ARQZ-R7 Datasheet(HTML) 12 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Descarga

Enlace URL