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ADT7463ARQZ-R7 Datasheet(PDF) 13 Page - ON Semiconductor |
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ADT7463ARQZ-R7 Datasheet(HTML) 13 Page - ON Semiconductor |
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13 / 52 page  REV. C –12– ADT7463 ADT7463 WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7463 are discussed below. The following abbreviations are used in the diagrams: S – START P– STOP R– READ W – WRITE A– ACKNOWLEDGE A – NO ACKNOWLEDGE The ADT7463 uses the following SMBus write protocols. Send Byte In this operation, the master device sends a single command byte to a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. For the ADT7463, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address. This is illustrated in Figure 10. S SLAVE ADDRESS WA A P 1 2 3 4 56 REGISTER ADDRESS Figure 10. Setting a Register Address for Subsequent Read If it is required to read data from the register immediately after setting up the address, the master can assert a repeat start con- dition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition. Write Byte In this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA to end the transaction. This is illustrated in Figure 11. S SLAVE ADDRESS WA 1 2 3 4 56 A DATA AP 78 REGISTER ADDRESS Figure 11. Single Byte Write to a Register ADT7463 READ OPERATIONS The ADT7463 uses the following SMBus read protocols. Receive Byte This is useful when repeatedly reading a single register. The register address needs to have been set up previously. In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. The master asserts a stop condition on SDA and the trans- action ends. In the ADT7463, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. S SLAVE ADDRESS RA DATA A P 1 2 3 4 56 Figure 12. Single Byte Read from a Register ALERT RESPONSE ADDRESS Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as an interrupt output or can be used as an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device’s SMBALERT line goes low, the following procedure occurs: 1. SMBALERT is pulled low. 2. Master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and it can be interrogated in the usual way. 4. If more than one device’s SMBALERT output is low, the one with the lowest device address will have priority in accordance with normal SMBus arbitration. 5. Once the ADT7463 has responded to the alert response address, the master must read the status registers and the SMBALERT will only be cleared if the error condition has gone away. SMBUS TIMEOUT The ADT7463 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7463 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled. CONFIGURATION REGISTER 1 – Register 0x40 <6> TODIS = 0; SMBus Timeout ENABLED (Default) <6> TODIS = 1; SMBus Timeout DISABLED REV. C ADT7463 –13– VOLTAGE MEASUREMENT INPUTS The ADT7463 has four external voltage measurement channels. It can also measure its own supply voltage, VCC. Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V supplies and the processor core voltage VCCP (0 V to 3 V input). The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). Setting Bit 7 of Configuration Register 1 (Reg. 0x40) allows a 5 V supply to power the ADT7463 and be measured without overranging the VCC measurement channel. The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. ANALOG-TO-DIGITAL CONVERTER (ADC) All analog inputs are multiplexed into the on-chip, successive approximation, ADC. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenu- ators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow for the tolerance of these supply voltages, the ADC pro- duces an output of 3/4 full scale (decimal 768 or 300 hex) for the nominal input voltage and so has adequate headroom to cope with overvoltages. INPUT CIRCUITRY The internal structure for the analog inputs is shown in Figure 13. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order, low-pass filter that gives the input immunity to high frequency noise. VOLTAGE MEASUREMENT REGISTERS Reg. 0x20 2.5 V Reading = 0x00 Default Reg. 0x21 VCCP Reading = 0x00 Default Reg. 0x22 VCC Reading = 0x00 Default Reg. 0x23 5 V Reading = 0x00 Default Reg. 0x24 12 V Reading = 0x00 Default VOLTAGE MEASUREMENT LIMIT REGISTERS Associated with each voltage measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Reg. 0x44 2.5 V Low Limit = 0x00 Default Reg. 0x45 2.5 V High Limit = 0xFF Default Reg. 0x46 VCCP Low Limit = 0x00 Default Reg. 0x47 VCCP High Limit = 0xFF Default Reg. 0x48 VCC Low Limit = 0x00 Default Reg. 0x49 VCC High Limit = 0xFF Default Reg. 0x4A 5 V Low Limit = 0x00 Default Reg. 0x4B 5 V High Limit = 0xFF Default Reg. 0x4C 12 V Low Limit = 0x00 Default Reg. 0x4D 12 V High Limit = 0xFF Default 30pF 120k� 30pF 93k� MUX 30pF 68k� 30pF 45k� 52.5k� 35pF 17.5k� 94k� 71k� 47k� 20k� 12VIN 5VIN 3.3VIN 2.5VIN VCCP Figure 13. Structure of Analog Inputs Table II shows the input ranges of the analog inputs and output codes of the 10-bit ADC. When the ADC is running, it samples and converts a voltage input in 711 µs and averages 16 conversions to reduce noise; a measurement on each input takes nominally 11.38 ms. REV. C ADT7463 –13– VOLTAGE MEASUREMENT INPUTS The ADT7463 has four external voltage measurement channels. It can also measure its own supply voltage, VCC. Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V supplies and the processor core voltage VCCP (0 V to 3 V input). The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). Setting Bit 7 of Configuration Register 1 (Reg. 0x40) allows a 5 V supply to power the ADT7463 and be measured without overranging the VCC measurement channel. The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. ANALOG-TO-DIGITAL CONVERTER (ADC) All analog inputs are multiplexed into the on-chip, successive approximation, ADC. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenu- ators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow for the tolerance of these supply voltages, the ADC pro- duces an output of 3/4 full scale (decimal 768 or 300 hex) for the nominal input voltage and so has adequate headroom to cope with overvoltages. INPUT CIRCUITRY The internal structure for the analog inputs is shown in Figure 13. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order, low-pass filter that gives the input immunity to high frequency noise. VOLTAGE MEASUREMENT REGISTERS Reg. 0x20 2.5 V Reading = 0x00 Default Reg. 0x21 VCCP Reading = 0x00 Default Reg. 0x22 VCC Reading = 0x00 Default Reg. 0x23 5 V Reading = 0x00 Default Reg. 0x24 12 V Reading = 0x00 Default VOLTAGE MEASUREMENT LIMIT REGISTERS Associated with each voltage measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Reg. 0x44 2.5 V Low Limit = 0x00 Default Reg. 0x45 2.5 V High Limit = 0xFF Default Reg. 0x46 VCCP Low Limit = 0x00 Default Reg. 0x47 VCCP High Limit = 0xFF Default Reg. 0x48 VCC Low Limit = 0x00 Default Reg. 0x49 VCC High Limit = 0xFF Default Reg. 0x4A 5 V Low Limit = 0x00 Default Reg. 0x4B 5 V High Limit = 0xFF Default Reg. 0x4C 12 V Low Limit = 0x00 Default Reg. 0x4D 12 V High Limit = 0xFF Default 30pF 120k� 30pF 93k� MUX 30pF 68k� 30pF 45k� 52.5k� 35pF 17.5k� 94k� 71k� 47k� 20k� 12VIN 5VIN 3.3VIN 2.5VIN VCCP Figure 13. Structure of Analog Inputs Table II shows the input ranges of the analog inputs and output codes of the 10-bit ADC. When the ADC is running, it samples and converts a voltage input in 711 µs and averages 16 conversions to reduce noise; a measurement on each input takes nominally 11.38 ms. REV. C ADT7463 –13– VOLTAGE MEASUREMENT INPUTS The ADT7463 has four external voltage measurement channels. It can also measure its own supply voltage, VCC. Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V supplies and the processor core voltage VCCP (0 V to 3 V input). The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). Setting Bit 7 of Configuration Register 1 (Reg. 0x40) allows a 5 V supply to power the ADT7463 and be measured without overranging the VCC measurement channel. The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. ANALOG-TO-DIGITAL CONVERTER (ADC) All analog inputs are multiplexed into the on-chip, successive approximation, ADC. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenu- ators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow for the tolerance of these supply voltages, the ADC pro- duces an output of 3/4 full scale (decimal 768 or 300 hex) for the nominal input voltage and so has adequate headroom to cope with overvoltages. INPUT CIRCUITRY The internal structure for the analog inputs is shown in Figure 13. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order, low-pass filter that gives the input immunity to high frequency noise. VOLTAGE MEASUREMENT REGISTERS Reg. 0x20 2.5 V Reading = 0x00 Default Reg. 0x21 VCCP Reading = 0x00 Default Reg. 0x22 VCC Reading = 0x00 Default Reg. 0x23 5 V Reading = 0x00 Default Reg. 0x24 12 V Reading = 0x00 Default VOLTAGE MEASUREMENT LIMIT REGISTERS Associated with each voltage measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Reg. 0x44 2.5 V Low Limit = 0x00 Default Reg. 0x45 2.5 V High Limit = 0xFF Default Reg. 0x46 VCCP Low Limit = 0x00 Default Reg. 0x47 VCCP High Limit = 0xFF Default Reg. 0x48 VCC Low Limit = 0x00 Default Reg. 0x49 VCC High Limit = 0xFF Default Reg. 0x4A 5 V Low Limit = 0x00 Default Reg. 0x4B 5 V High Limit = 0xFF Default Reg. 0x4C 12 V Low Limit = 0x00 Default Reg. 0x4D 12 V High Limit = 0xFF Default 30pF 120k� 30pF 93k� MUX 30pF 68k� 30pF 45k� 52.5k� 35pF 17.5k� 94k� 71k� 47k� 20k� 12VIN 5VIN 3.3VIN 2.5VIN VCCP Figure 13. Structure of Analog Inputs Table II shows the input ranges of the analog inputs and output codes of the 10-bit ADC. When the ADC is running, it samples and converts a voltage input in 711 µs and averages 16 conversions to reduce noise; a measurement on each input takes nominally 11.38 ms. Rev. 4 | Page 13 of 52 | www.onsemi.com |
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