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ADT7463ARQZ-R7 Datasheet(PDF) 3 Page - ON Semiconductor |
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ADT7463ARQZ-R7 Datasheet(HTML) 3 Page - ON Semiconductor |
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3 / 52 page ![]() REV. C ADT7463 –3– Parameter Min Typ Max Unit Test Conditions/Comment DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH 2.0 V 5.5 V Maximum Input Voltage Input Low Voltage, VIL +0.8 V –0.3 V Minimum Input Voltage Hysteresis 0.5 V p-p DIGITAL INPUT LOGIC LEVELS (THERM) AGTL+ Input High Voltage, VIH 0.75 � VCCP V Input Low Voltage, VIL 0.4 V DIGITAL INPUT CURRENT Input High Current, IIH –1 µAVIN = VCC Input Low Current, IIL +1 µAVIN = 0 Input Capacitance, CIN 5 pF SERIAL BUS TIMING5 Clock Frequency, fSCLK 400 kHz See Figure 1 Glitch Immunity, tSW 50 ns See Figure 1 Bus Free Time, tBUF 1.3 µsSee Figure 1 Start Setup Time, tSU;STA 0.6 µsSee Figure 1 Start Hold Time, tHD;STA 0.6 µsSee Figure 1 SCL Low Time, tLOW 1.3 µsSee Figure 1 SCL High Time, tHIGH 0.6 50 µsSee Figure 1 SCL, SDA Rise Time, tR 1000 ns See Figure 1 SCL, SDA Fall Time, tF 300 µsSee Figure 1 Data Setup Time, tSU;DAT 100 ns See Figure 1 Data Hold Time, tHD;DAT 300 ns See Figure 1 Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can Be Optionally Disabled NOTES 1All voltages are measured with respect to GND, unless otherwise specified. 2Typicals are at TA = 25°C and represent the most likely parametric norm. 3Logic inputs accept input high voltages up to VMAX even when the device is operating down to VMIN. 4Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. 5Guaranteed by design, not production tested. Specifications subject to change without notice. P S tSU;DAT tHIGH tF tHD;DAT tR tLOW tSU;STO PS SCL SDA tHD;STA tHD;STA tSU;STA tBUF Figure 1. Diagram for Serial Bus Timing Rev. 4 | Page 3 of 52 | www.onsemi.com |
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