ADT7463ARQZ-R7 datasheet(21/52 Pages) ONSEMI

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REV. C

ADT7463

–21–

OOL = 1 DENOTES A PARAMETER

MONITORED THROUGH STATUS REG 2

IS OUT-OF-LIMIT

10000000

Read/Write

(Click

Digits)

OOL

R2T

R1T

CCP

2.5V

Figure 21. Status Register 1

Status Register 1 (Reg. 0x41)

Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and

Status Register 2 should be read.

Bit 6 (R2T) = 1, Remote 2 Temperature High or Low Limit

has been exceeded.

Bit 5 (LT) = 1, Local Temperature High or Low Limit has

been exceeded.

Bit 4 (R1T) = 1, Remote 1 Temperature High or Low Limit

has been exceeded.

Bit 3 (5V) = 1, 5 V High or Low Limit has been exceeded.

Bit 2 (VCC) = 1, VCC High or Low Limit has been exceeded.

Bit 1 (VCCP) = 1, VCCP High or Low Limit has been exceeded.

Bit 0 (2.5V) = 1, 2.5 V High or Low Limit has been exceeded.

F4P = 1, FAN4 OR THERM

TIMER IS OUT-OF-LIMIT

00100000

Read/Write

(Click

Digits)

F4P

FAN3

FAN2

FAN1

OVT

12V/VC

Figure 22. Status Register 2

Status Register 2 (Reg. 0x42)

Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.

Bit 6 (D1) = 1, indicates an open or short on D2+/D2– inputs.

Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum

speed. Alternatively, indicates that THERM limit has been

exceeded if the THERM function is used.

Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below mini-

mum speed.

Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum

speed.

Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below mini-

mum speed.

Bit 1 (OVT) = 1, indicates that a THERM overtemperature

limit has been exceeded.

Bit 0 (12V/VC) = 1, 12 V High or Low Limit has been

exceeded. If the VID code change function is used, this bit

indicates a change in VID code on the VID0 to VID5 inputs.

SMBALERT Interrupt Behavior

The ADT7463 can be polled for status, or an SMBALERT

interrupt can be generated for out-of-limit conditions. It is

important to note how the SMBALERT output and status bits

behave when writing Interrupt Handler software.

“STICKY”

STATUS

BIT

HIGH LIMIT

TEMPERATURE

SMBALERT

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

Figure 23. SMBALERT and Status Bit Behavior

Figure 23 shows how the SMBALERT output and “sticky” status

bits behave. Once a limit is exceeded, the corresponding status

bit gets set to 1. The status bit remains set until the error condi-

tion subsides and the status register gets read. The status bits are

referred to as sticky since they remain set until read by software.

This ensures that an out-of-limit event cannot be missed if software

is polling the device periodically. Note that the SMBALERT

output remains low for the entire duration that a reading is

out-of-limit and until the status register has been read. This

has implications on how software handles the interrupt.

HANDLING SMBALERT INTERRUPTS

To prevent the system from being tied up servicing interrupts, it

is recommend to handle the SMBALERT interrupt as follows:

1. Detect the SMBALERT assertion.

2. Enter the interrupt handler.

3. Read the status registers to identify the interrupt source.

4. Mask the interrupt source by setting the appropriate mask

bit in the interrupt mask registers (Reg. 0x74, 0x75).

5. Take the appropriate action for a given interrupt source.

6. Exit the Interrupt Handler.

7. Periodically poll the status registers. If the interrupt status bit

has cleared, reset the corresponding interrupt mask bit to 0.

This causes the SMBALERT output and status bits to be-

have as shown in Figure 24.

“STICKY”

STATUS

BIT

HIGH LIMIT

TEMPERATURE

SMBALERT

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

INTERRUPT

MASK BIT SET

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

Figure 24. How Masking the Interrupt Source Affects

SMBALERT Output

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