ADT7463ARQZ-R7 datasheet(39/52 Pages) ONSEMI

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REV. C

ADT7463

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Table XIV. Register 0x42 – Interrupt Status Register 2 (Power-On Default = 0x00)

Bit

Name

R/W

Description

<0>

12V/VC

Read-Only

A one indicates the 12 V high or low limit has been exceeded. This bit gets cleared on a read

of the status register only if the error condition has subsided. If Pin 21 is configured as VID5,

this bit is the VID change bit. This bit gets set when the levels on VID0 to VID5 are different

than they were 11

µs previously. This can be used to generate an SMBALERT whenever

the VID code changes.

<1>

OVT

Read-Only

A one indicates that one of the THERM overtemperature limits has been exceeded. This

bit gets cleared on a read of the status register when the temperature drops below

THERM – THYST.

<2>

FAN1

Read-Only

A one indicates that Fan 1 has dropped below minimum speed or has stalled.

This bit does NOT get set when the PWM 1 output is off.

<3>

FAN2

Read-Only

A one indicates that Fan 2 has dropped below minimum speed or has stalled.

This bit does NOT get set when the PWM 2 output is off.

<4>

FAN3

Read-Only

A one indicates that Fan 3 has dropped below minimum speed or has stalled.

This bit does NOT get set when the PWM 3 output is off.

<5>

F4P

Read-Only

A one indicates that Fan 4 has dropped below minimum speed or has stalled.

This bit does NOT get set when the PWM 3 output is off.

Read-Only

If Pin 14 or Pin 20 is configured as the THERM timer input for THERM

monitoring, then this bit gets set when the THERM assertion time exceeds the

limit programmed in the THERM Limit Register (Reg. 0x7A).

<6>

Read-Only

A one indicates either an open or short circuit on the Thermal Diode 1 inputs.

<7>

Read-Only

A one indicates either an open or short circuit on the Thermal Diode 2 inputs.

Table XV. Register 0x43 – VID Register (Power-On Default = 0x00)

Bit

Name

R/W

Description

<4:0>

VID[4:0]

Read-Only

The VID[4:0] inputs from the CPU to indicate the expected processor core voltage. On

power-up, these bits reflect the state of the VID pins even if monitoring is not enabled.

<5>

VID5

Read-Only

Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, then the VID5 bit always

reads back 0 (power-on default).

<6>

THLD

Read/Write

This selects the input switching threshold for the VID inputs. THLD = 0 selects a

threshold of 1 V (VOL < 0.8 V, VIH > 1.7 V). THLD = 1 lowers the switching threshold

to 0.6 V (VOL < 0.4 V, VIH > 0.8 V).

<7>

VIDSEL

Read/Write

VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).

VIDSEL = 1 configures Pin 21 as the VID5 input. This also allows VID code

changes to be detected.

Table XVI. Voltage Limit Registers

R/W

Description

Power-On Default

0x44

Read/Write

2.5 V Low Limit

0x00

0x45

Read/Write

2.5 V High Limit

0xFF

0x46

Read/Write

VCCP Low Limit

0x00

0x47

Read/Write

VCCP High Limit

0xFF

0x48

Read/Write

VCC Low Limit

0x00

0x49

Read/Write

VCC High Limit

0xFF

0x4A

Read/Write

5 V Low Limit

0x00

0x4B

Read/Write

5 V High Limit

0xFF

0x4C

Read/Write

12 V Low Limit

0x00

0x4D

Read/Write

12 V High Limit

0xFF

Setting the Configuration Register 1 Lock bit has no effect on these registers.

High Limits: An interrupt is generated when a value exceeds its high limit (> comparison).

Low Limits: An interrupt is generated when a value is equal to or below its low limit (

≤ comparison).

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