RM0319 datasheet(109/368 Pages) STMICROELECTRONICS

109 / 368 page

RM0319

External memory interface (EMI)

Doc ID 022640 Rev 3

109/368

Control Register (control_0_reg, as it is connected to CS0) contents would be: 0x1

(Bit [1:0] = 01 indicates 16 bit, Bit 2 = 0 indicates that unequal bus size access is not

supported, Bit 3 = 0 indicates that the data available on the lower byte of peripheral bus.)

No Acknowledgement, so Ack_reg content would be: 0x1.

(As it is connected to CS0, Bit 0 of Ack_reg should be 1 indicating ACK behavior not used.)

Timing registers to be programmed are tSCS_0_reg, tSE_0_reg, tENw_0_reg, tENr_0_reg

and tDCS_0_reg. The timing mentioned in these registers should be expressed in number

of AHB cycles.

As a 16 bit peripheral is connected, only 16 bit accesses are supported from AHB. If not so,

an AHB Error is indicated. An interrupt is also raised.

Example 2: An 8-bit peripheral following byte lane procedure during read and write is

connected on CS3.

Control Register: control_3_reg = 0x0C.

(Bit [1:0] = 00 indicates 8 bits, Bit 2 = 1 indicates byte lane procedure used, Bit 3 = 1

indicates data available in corresponding lanes and Bit 4 = 0 indicates little endian data.

Ack_Reg: 0x0. Bit 3= 0 indicating ACK behaviour is used.

Timeout_reg = 0xABC. As ACK behavior is used, the timeout register should be

programmed accordingly. Here a random value is given as an example. It should be

replaced with an appropriate value. The default value is 0xFF. If timeout occurs, an AHB

error and its associated interrupt are generated.

The timing registers to be programmed are tSCS_3_reg, tSE_3_reg, tENw_3_reg,

tENr_3_reg and tDCS_3_reg. The timing mentioned in these registers should be expressed

in number of AHB cycles.

As 8-bit peripheral is connected, only 8-bit accesses are allowed.

RM0319 Datasheet(PDF) 109 Page - STMicroelectronics