RM0319 datasheet(110/368 Pages) STMICROELECTRONICS

110 / 368 page

USB 2.0 Host ports (UHC)

RM0319

110/368

Doc ID 022640 Rev 3

USB 2.0 Host ports (UHC)

This chapter focuses on USB Host functionality and operation.

For technical details about the programmable registers related to the USB Host, refer to the

USB Host registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

10.1

Overview

SPEAr320S provides a USB 2.0 Host with 2 physical ports which are fully compliant with the

Universal Serial Bus specification (version 2.0), offering an interface to the industry-

standard AHB bus.

10.2

Main features

●

A PHY interface implementing a USB 2.0 Transceiver Macro-cell Interface plus

(UTMI+) fully compliant with UTMI+ specification (revision 1.0), to execute serialization

and de-serialization of transmissions over the USB line.

●

Either 30 MHz clock for 16-bit interface or 60 MHz for 8-bit interface are supported by

the UTMI+ PHY interface.

●

A USB 2.0 Host Controller (UHC) which is connected to the AHB bus and generates

the commands for the UTMI+ PHY.

●

The UHC complies with both the Enhanced Host Controller Interface (EHCI)

specification (version 1.0) and the Open Host Controller Interface (OHCI) specification

(version 1.0a).

●

The UHC supports the 480 Mbps high-speed (HS) for USB 2.0 through an embedded

EHCI Host Controller, The EHCI controller is able to sustain HS communications over

the 2 ports in parallel.

●

The UHC supports the 12 Mbps full-speed (FS) and the 1.5 Mbps low-speed (LS) for

USB 1.1 through two integrated OHCI Host Controllers.

●

All clock synchronization is handled within the UHC.

●

An AHB slave for each controller (1 EHCI and 2 OHCI), acting as programming

interface to access to control and status registers.

●

An AHB master for each controller (1 EHCI and 2 OHCI) for data transfer to system

memory, supporting 8, 16, and 32 bit wide data transactions on the AHB bus.

●

32-bit AHB bus addressing

The Host controller is capable of managing two different devices at a time (each one in

EHCI or OHCI mode) over the two PHY interfaces.

The Host subsystem can manage an external power switch, providing a control line to

enable or disable the power, and an input line to sense any over-current condition detected

by the external switch.

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