AD9880SLASHPCB datasheet(38/64 Pages) AD

38 / 64 page

AD9880

Rev. 0 | Page 38 of 64

0x04 7-3

Phase Adjust

These bits provide a phase adjustment for the DLL to

generate the ADC clock. A 5-bit value that adjusts the

sampling phase in 32 steps across one pixel time. Each

step represents an 11.25° shift in sampling phase. The

power up default is 16.

INPUT GAIN

0x05

7-0

Red Channel Gain

These bits control the programmable gain amplifier

(PGA) of the red channel. The AD9880 can accom-

modate input signals with a full-scale range of

between 0.5 V and 1.0 V p-p. Setting the red gain to

255 corresponds to an input range of 1.0 V. A red gain

of 0 establishes an input range of 0.5 V. Note that

increasing red gain results in the picture having less

contrast (the input signal uses fewer of the available

converter codes). The power-up default is 0x80.

0x06

7-0

Green Channel Gain

These bits control the PGA of the green channel. The

AD9880 can accommodate input signals with a full-

scale range of between 0.5 V and 1.0 V p-p. Setting the

green gain to 255 corresponds to an input range of 1.0

V. A green gain of 0 establishes an input range of 0.5 V.

Note that increasing green gain results in the picture

having less contrast (the input signal uses fewer of the

available converter codes). The power-up default is

0x80.

0x07

7-0

Blue Channel Gain

These bits control the PGA of the blue channel. The

AD9880 can accommodate input signals with a full-

scale range of between 0.5 V and 1.0 V p-p. Setting the

blue gain to 255 corresponds to an input range of

1.0 V. A blue gain of 0 establishes an input range of

0.5 V. Note that increasing blue gain results in the

picture having less contrast (the input signal uses

fewer of the available converter codes). The power-up

default is 0x80.

INPUT OFFSET

0x08

7-0

Red Channel Offset Adjust

If clamp feedback is enabled, the 8-bit offset adjust

determines the clamp code. The 8-bit offset adjust is a

twos complement number consisting of 1 sign bit plus

7 bits (0x7F = +127, 0x00 = 0, 0xFF = −1, and 0x80 =

−128). For example, if the register is programmed to

130d, then the output code is equal to 130d at the end

of the clamp period. Note that incrementing the offset

regardless of the clamp feedback setting.

The power-up default is 0.

0x09

7-0

Red Channel Offset

These eights bits are the red channel offset control.

The offset control shifts the analog input, resulting in

a change in brightness. Note that the function of the

offset register depends on whether clamp feedback is

enabled (Register 0x1C, Bit 7 = 1).

If clamp feedback is disabled, the offset register bits

control the absolute offset added to the channel. The

offset control provides a +127/−128 LSBs of adjust-

ment range, with one LSB of offset corresponding to

1 LSB of output code. If clamp feedback is enabled

these bits provide the relative offset (brightness) from

the offset adjust in the previous register. The power-up

default is 0x80.

0x0A

7-0

Green Channel Offset Adjust

If clamp feedback is enabled, the 8-bit offset adjust

determines the clamp code. The 8-bit offset adjust is a

twos complement number consisting of 1 sign bit plus

7 bits (0x7F = +127, 0x00 = 0, 0xFF = −1, and 0x80 =

−128). For example, if the register is programmed to

130d, then the output code is equal to 130d at the end

of the clamp period. Note that incrementing the offset

less of the clamp feedback setting. The power-up

default is 0.

0x0B

7-0

Green Channel Offset

These eight bits are the green channel offset control.

The offset control shifts the analog input, resulting in

a change in brightness. Note that the function of the

offset register depends on whether clamp feedback is

enabled (Register 0x1C, Bit 7 = 1).

If clamp feedback is disabled, the offset register bits

control the absolute offset added to the channel. The

offset control provides a +127/−128 LSBs of adjust-

ment range, with one LSB of offset corresponding to

1 LSB of output code. If clamp feedback is enabled

these bits provide the relative offset (brightness) from

the offset adjust in the previous register. The power-up

default is 0x80.

0x0C

7-0

Blue Channel Offset Adjust

If clamp feedback is enabled, the 8-bit offset adjust

determines the clamp code. The 8-bit offset adjust is a

twos complement number consisting of 1 sign bit plus

7 bits (0x7F = +127, 0x00 = 0, 0xFF = −1, and 0x80 =

−128). For example, if the register is programmed to

130d, then the output code is equal to 130d at the end

of the clamp period. Note that incrementing the offset

less of the clamp feedback setting. The power-up

default is 0.

AD9880/PCB Datasheet(PDF) 38 Page - Analog Devices

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