AD9880SLASHPCB datasheet(43/64 Pages) AD

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AD9880

Rev. 0 | Page 43 of 64

0x20

7-0

Sync Filter Window Width

This 8-bit register sets the distance in 40 MHz clock

periods (25 ns), which is the allowed distance for

Hsync pulses before and after the expected Hsync

edge. This is the heart of the filter in that it only looks

for Hsync pulses at a given time (plus or minus this

window) and then ignores extraneous equalization

pulses that disrupt accurate PLL operation. The

power-up default setting is 10d, or 200 ns on either

side of the expected Hsync.

0x21

Sync Processing Filter Enable

This bit selects which Hsync is used for the sync

processing functions of internal Coast, H/V count,

field detection, and Vsync duration counts. A clean

Hsync is fundamental to accurate processing of the

sync. The power-up default setting is 1.

Table 35. Sync Processing Filter Enable

Select

Result

Sync processing uses raw Hsync or SOG

Sync processing uses regenerated Hsync from sync

filter

0x21

PLL Sync Filter Enable

This bit selects which signal the PLL uses. It can select

between raw Hsync or SOG, or filtered versions. The

filtering of the Hsync and SOG can eliminate nearly

all extraneous transitions which have traditionally

caused PLL disruption. The power-up default setting

is 0.

Table 36. PLL Sync Filter Enable

Select

Result

PLL uses raw Hsync or SOG inputs

PLL uses filtered Hsync or SOG inputs

0x21

Vsync Filter Enable

The purpose of the Vsync filter is to guarantee the

position of the Vsync edge with respect to the Hsync

edge and to generate a field signal. The filter works by

examining the placement of Vsync and regenerating a

correctly placed Vsync one line later. The Vsync is

first checked to see whether it occurs in the Field 0

position or the Field 1 position. This is done by

checking the leading edge position against the sync

separator threshold and the Hsync position. The

Hsync width is divided into four quadrants with

Quadrant 1 starting at the Hsync leading edge plus a

sync separator threshold. If the Vsync leading edge

occurs in Quadrant 1 or 4 then the field is set to 0 and

the output Vsync is placed coincident with the Hsync

leading edge. If the Vsync leading edge occurs in

Quadrant 2 or 3 then the field is set to 1 and the

output Vsync leading edge is placed in the center of

the line. In this way, the Vsync filter creates a

predictable relative position between Hsync and

Vsync edges at the output.

If the Vsync occurs near the Hsync edge, this guaran-

tees that the Vsync edge follows the Hsync edge. This

performs filtering also in that it requires a minimum

of 64 lines between Vsyncs. The Vsync filter cleans up

extraneous pulses that might occur on the Vsync. This

should be enabled whenever the Hsync/Vsync count is

used. Setting this bit to 0 disables the Vsync filter.

Setting this bit to 1 enables the Vsync filter. Power-up

default is 0.

Table 37. Vsync Filter Enable

Vsync Filter Bit

Result

Vsync filter disabled

Vsync filter enabled

0x21

Vsync Duration Enable

This enables the Vsync duration block which is

designed to be used with the Vsync filter. Setting the

bit to 0 leaves the Vsync output duration unchanged;

setting the bit to 1 sets the Vsync output duration

based on Register 0x22. The power-up default is 0.

Table 38. Vsync Duration Enable

Vsync

Duration Bit

Result

Vsync output duration unchanged

Vsync output duration set by 0x22

0x21

Auto Offset Clamp Mode

This bit specifies if the auto offset measurement takes

place during clamp or either 10 or 16 clocks afterward.

The measurement takes 6 clock cycles.

Table 39. AO Clamp Mode

Offset Mode

Result

Auto offset measurement takes place during

clamp period

Auto offset measurement is set by 0x21, Bit 2

0x21

Auto Offset Clamp Length

This bit sets the delay following the end of the clamp

period for AO measurement. This bit is valid only if

Table 40. AO Clamp Length

AO Offset

Clamp Bit

Result

Delay is 10 clock cycles

Delay is 16 clock cycles

0x22

7-0

Vsync Duration

This is used to set the output duration of the Vsync,

and is designed to be used with the Vsync filter. This

is valid only if Register 0x21, Bit 4 is set to 1. Power-up

default is 4.

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