AD9880SLASHPCB datasheet(56/64 Pages) AD

56 / 64 page

AD9880

Rev. 0 | Page 56 of 64

2-WIRE SERIAL CONTROL PORT

A 2-wire serial interface control interface is provided in the

AD9880. Up to two AD9880 devices can be connected to the

2-wire serial interface, with a unique address for each device.

The 2-wire serial interface comprises a clock (SCL) and a

bidirectional data (SDA) pin. The analog flat panel interface

acts as a slave for receiving and transmitting data over the serial

interface. When the serial interface is not active, the logic levels

on SCL and SDA are pulled high by external pull-up resistors.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is low. If SDA changes state while SCL is

high, the serial interface interprets that action as a start or stop

sequence.

There are six components to serial bus operation:

•

Start signal

•

Slave address byte

•

Base register address byte

•

Data byte to read or write

•

Stop signal

•

Acknowledge (Ack)

When the serial interface is inactive (SCL and SDA are high)

communications are initiated by sending a start signal. The start

signal is a high-to-low transition on SDA while SCL is high.

This signal alerts all slaved devices that a data transfer sequence

is coming.

The first eight bits of data transferred after a start signal

comprise a seven bit slave address (the first seven bits) and a

single R/W\ bit (the eighth bit). The R/W\ bit indicates the

direction of data transfer, read from (1) or write to (0) the slave

device. If the transmitted slave address matches the address of

the device (set by the state of the SA0 input pin as shown in

Table 97), the AD9880 acknowledges by bringing SDA low on

the 9th SCL pulse. If the addresses do not match, the AD9880

does not acknowledge.

Table 97. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

A6 (MSB)

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit of

the sequence.

If the AD9880 does not acknowledge the master device during a

write sequence, the SDA remains high so the master can gener-

ate a stop signal. If the master device does not acknowledge the

AD9880 during a read sequence, the AD9880 interprets this as

end of data. The SDA remains high, so the master can generate

a stop signal.

Writing data to specific control registers of the AD9880 requires

that the 8-bit address of the control register of interest be writ-

ten after the slave address has been established. This control

tions. The base address auto-increments by one for each byte of

data written after the data byte intended for the base address. If

more bytes are transferred than there are available addresses,

the address does not increment and remains at its maximum

value. Any base address higher than the maximum value does

not produce an acknowledge signal.

Data are read from the control registers of the AD9880 in a

similar manner. Reading requires two data transfer operations:

The base address must be written with the R/W bit of the slave

address byte low to set up a sequential read operation.

Reading (the R/W bit of the slave address byte high) begins at

the previously established base address. The address of the read

To terminate a read/write sequence to the AD9880, a stop signal

must be sent. A stop signal comprises a low-to-high transition

of SDA while SCL is high.

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first genera-

ting a stop signal to terminate the current communication. This

is used to change the mode of communication (read, write)

between the slave and master without releasing the serial

interface lines.

AD9880/PCB Datasheet(PDF) 56 Page - Analog Devices

AD9880/PCB Datasheet(HTML) 56 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Descarga

Enlace URL