AD9880SLASHPCB datasheet(26/64 Pages) AD

26 / 64 page

AD9880

Rev. 0 | Page 26 of 64

Hex

Address

Read/Write

or Read Only

Bits

Default

Value

Description

[6]

*1******

PLL Sync Filter Enable

Enables the PLL to use the filtered Hsync rather than the raw

Hsync. This clips any bad Hsyncs, but does not regenerate

missing pulses.

[5]

**0*****

Vsync Filter Enable

Enables the Vsync filter. The Vsync filter gives a predictable

Hsync/Vsync timing relationship but clips one Hsync period off

the leading edge of Vsync.

[4]

***0****

Vsync Duration

Enable

Enables the Vsync duration block. This block can be used if

necessary to restore the duration of a filtered Vsync.

[3]

**** 1***

Auto Offset Clamp

Mode

0 = auto offset measures code during clamp.

1 = auto offset measures code (10 or 16) clock cycles after end of

clamp for 6 clock cycles.

[2]

**** *1**

Auto Offset Clamp

Length

Sets delay after end of clamp for auto offset clamp mode = 1.

0 = Delay is 10 clock cycles.

1 = Delay is 16 clock cycles.

0x22

Read/Write

[7:0]

Vsync Duration

Vsync Duration.

0x23

Read/Write

[7:0]

Hsync Duration

Hsync Duration. Sets the duration of the output Hsync in pixel

clocks.

0x24

Read/Write

[7]

1*******

Hsync Output

Polarity

Output Hsync Polarity (both DVI and Analog). 0 = active low out.

1 = active high out.

[6]

*1******

Vsync Output Polarity

Output Vsync polarity (both DVI and analog).

0 = active low out.

1 = active high out.

[5]

**1*****

DE Output Polarity

Output DE polarity (both DVI and analog) .

0 = active low out.

1 = active high out.

[4]

***1****

Field Output Polarity

Output field polarity (both DVI and analog).

0 = active low out.

1 = active high out.

[3]

****1***

SOG Output Polarity

Output SOG polarity (analog only).

0 = active low out.

1 = active high out.

[2:1]

*****11*

SOG Output Select

Selects signal present on SOG output.

00 = SOG (SOG0 or SOG1).

01 = Raw Hsync (HSYNC0 or HSYNC1).

10 = Regenerated sync.

11 = Hsync to PLL.

[0]

*******0

Output CLK Invert

0 = Don’t invert clock out.

1 = Invert clock out.

0x25

Read/Write

[7:6]

01******

Output CLK Select

Select which clock to use on output pin. 1× CLK is divided down

from TMDS clock input when pixel repetition is in use.

00 = ½× CLK.

01 = 1× CLK.

10 = 2× CLK.

11 = 90° phase 1X CLK.

[5:4]

**11****

Output Drive

Strength

Set the drive strength of the outputs.

00 = lowest, 11 = highest.

[3:2]

****00**

Output Mode

Selects which pins the data comes out on.

00 = 4:4:4 mode (normal).

01 = 4:2:2 + DDR 4:2:2 on blue.

10 = DDR 4:4:4 + DDR 4:2:2 on blue.

AD9880/PCB Datasheet(PDF) 26 Page - Analog Devices

AD9880/PCB Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Descarga

Enlace URL