AD9880SLASHPCB datasheet(27/64 Pages) AD

27 / 64 page

AD9880

Rev. 0 | Page 27 of 64

Hex

Address

Read/Write

or Read Only

Bits

Default

Value

Description

11 = 12-bit 4:2:2 (HDMI can have 12-bit 4:2:2 data).

[1]

******1*

Primary Output

Enable

Enables primary output.

[0]

*******0

Secondary Output

Enable

Enables secondary output (DDR 4:2:2 in Output Modes 1 and 2).

0x26

Read/Write

[7]

0*******

Output Three-State

Three-state the outputs.

[6]

*0******

SOG Three-State

Three-state the SOG output.

[5]

**0*****

SPDIF Three-State

Three-state the SPDIF output.

[4]

***0****

I2S Three-State

Three-state the I2S output and the MCLK out.

[3]

****1***

Power-Down Pin

Polarity

Sets polarity of power-down pin.

0 = active low.

1 = active high.

Selects the function of the power-down pin.

[2:1]

*****00*

Power-Down Pin

Function

00 = power-down.

01 = power-down and three-state SOG.

10 = three-state outputs only.

11 = three-state outputs and SOG.

[0]

*******0

Power-Down

0 = normal.

1 = power-down.

0x27

Read/Write

[7]

1*******

Auto Power-Down

Enable

0 = disable auto low power state.

1 = enable auto low power state.

[6]

*0******

HDCP A0

Sets the LSB of the address of the HDCP I2C. Set to 1 only for a

second receiver in a dual-link configuration.

0 = Use internally generated MCLK.

1 = Use external MCLK input.

[5]

**0*****

MCLK External

Enable

If an external MCLK is used then it must be locked to the video

clock according to the CTS and N available in the I2C. Any mis-

match between the internal MCLK and the input MCLK results in

dropped or repeated audio samples.

[4]

***0****

BT656 EN

Enables EAV/SAV codes to be inserted into the video output

data.

[3]

****0***

Force DE Generation

Allows use of the internal DE generator in DVI mode.

[2:0]

*****000

Interlace Offset

Sets the difference (in Hsyncs) in field length between Field 0

and Field 1.

0x28

Read/Write

[7:2]

011000**

VS Delay

Sets the delay (in lines) from Vsync leading edge to the start of

active video.

[1:0]

******01

HS Delay MSB

MSB, Register 0x29.

0x29

Read/Write

[7:0]

00000100

HS Delay

Sets the delay (in pixels) from Hsync leading edge to the start of

active video.

0x2A

Read/Write

[3:0]

****0101

Line Width MSB

MSB, Register 0x2B.

0x2B

Read/Write

[7:0]

00000000

Line Width

Sets the width of the active video line (in pixels).

0x2C

Read/Write

[3:0]

****0010

Screen Height MSB

MSB, Register 0x2D.

0x2D

Read/Write

[7:0]

11010000

Screen Height

Sets the height of the active screen (in lines).

0x2E

Read/Write

[7]

0*******

Ctrl EN

Allows Ctrl [3:0] to be output on the I2s data pins.

00 = I2S mode.

[6:5]

*00*****

I2S Out Mode

01 = right-justified.

10 = left-justified.

11 = raw IEC60958 mode.

[4:0]

***11000

I2S Bit Width

Sets the desired bit width for right-justified mode.

AD9880/PCB Datasheet(PDF) 27 Page - Analog Devices

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