AD9880SLASHPCB datasheet(16/64 Pages) AD

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AD9880

Rev. 0 | Page 16 of 64

TIMING

The output data clock signal is created so that its rising edge

always occurs between data transitions and can be used to latch

the output data externally.

There is a pipeline in the AD9880, which must be flushed

before valid data becomes available. This means 23 data sets are

presented before valid data is available.

The timing diagram in Figure 7 shows the operation of the

AD9880.

tPER

tDCYCLE

tSKEW

DATACK

DATA

HSOUT

Figure 7. Output Timing

Hsync Timing

Horizontal Sync (Hsync) is processed in the AD9880 to

eliminate ambiguity in the timing of the leading edge with

respect to the phase-delayed pixel clock and data.

The Hsync input is used as a reference to generate the pixel

sampling clock. The sampling phase can be adjusted, with

respect to Hsync, through a full 360° in 32 steps via the phase

adjust register (to optimize the pixel sampling time). Display

systems use Hsync to align memory and display write cycles, so

it is important to have a stable timing relationship between the

Hsync output (HSOUT) and data clock (DATACK).

Three things happen to Hsync in the AD9880. First, the polarity

of Hsync input is determined and thus has a known output

polarity. The known output polarity can be programmed either

active high or active low (Register 0x24, Bit 7). Second, HSOUT

is aligned with DATACK and data outputs. Third, the duration

of HSOUT (in pixel clocks) is set via Register 0x23. HSOUT is

the sync signal that should be used to drive the rest of the

display system.

Coast Timing

In most computer systems, the Hsync signal is provided

continuously on a dedicated wire. In these systems, the Coast

input and function are unnecessary, and should not be used and

the pin should be permanently connected to the inactive state.

In some systems, however, Hsync is disturbed during the verti-

cal sync period (Vsync). In some cases, Hsync pulses disappear.

In other systems, such as those that employ composite sync

(Csync) signals or embedded SOG, Hsync includes equalization

pulses or other distortions during Vsync. To avoid upsetting the

clock generator during Vsync, it is important to ignore these

distortions. If the pixel clock PLL sees extraneous pulses, it

attempts to lock to this new frequency, and changes frequency

by the end of the Vsync period. It then takes a few lines of

correct Hsync timing to recover at the beginning of a new

frame, resulting in a tearing of the image at the top of the

display.

The Coast input is provided to eliminate this problem. It is an

asynchronous input that disables the PLL input and allows the

clock to free run at its then-current frequency. The PLL can free

run for several lines without significant frequency drift.

Coast can be generated internally by the AD9880 (see

or can be provided externally by the graphics controller.

Sync Processing

The inputs of the sync processing section of the AD9880 are

combinations of digital Hsyncs and Vsyncs, analog sync-on-

green, or sync-on-Y signals, and an optional external Coast

signal. From these signals it generates a precise, jitter-free (9%

or less at 95 MHz) clock from its PLL; an odd-/even-field signal;

Hsync and Vsync out signals; a count of Hsyncs per Vsync; and

a programmable SOG output. The main sync processing blocks

are the sync slicer, sync separator, Hsync filter, Hsync regen-

erator, Vsync filter, and Coast generator.

The sync slicer extracts the sync signal from the green graphics

or luminance video signal that is connected to the SOGIN input

and outputs a digital composite sync. The sync separator’s task

is to extract Vsync from the composite sync signal, which can

come from either the sync slicer or the Hsync input. The Hsync

filter is used to eliminate any extraneous pulses from the Hsync

or SOGIN inputs, outputting a clean, low-jitter signal that is

appropriate for mode detection and clock generation. The

Hsync regenerator is used to recreate a clean, although not low

jitter, Hsync signal that can be used for mode detection and

counting Hsyncs per Vsync. The Vsync filter is used to elimi-

nate spurious Vsyncs, maintain a stable timing relationship

between the Vsync and Hsync output signals, and generate the

odd/even field output. The Coast generator creates a robust

Coast signal that allows the PLL to maintain its frequency in

the absence of Hsync pulses.

AD9880/PCB Datasheet(PDF) 16 Page - Analog Devices

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