AD9880SLASHPCB datasheet(18/64 Pages) AD

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AD9880

Rev. 0 | Page 18 of 64

Sync Separator

As part of sync processing, the sync separator’s task is to extract

Vsync from the composite sync signal. It works on the idea that

the Vsync signal stays active for a much longer time than the

Hsync signal. By using a digital low-pass filter and a digital

comparator, it rejects pulses with small durations (such as

Hsyncs and equalization pulses) and only passes pulses with

large durations, such as Vsync (see Figure 9).

The threshold of the digital comparator is programmable for

maximum flexibility. To program the threshold duration, write

a value (N) to Register 0x11. The resulting pulse width is

N × 200 ns. So, if N = 5 the digital comparator threshold is 1 μs.

Any pulses less than 1 μs is rejected, while any pulse greater

than 1 μs passes through.

The sync separator on the AD9880 is simply an 8-bit digital

counter with a 6 MHz clock. It works independently of the

polarity of the composite sync signal. Polarities are determined

elsewhere on the chip. The basic idea is that the counter counts

up when Hsync pulses are present. But since Hsync pulses are

relatively short in width, the counter only reaches a value of N

before the pulse ends. It then starts counting down until

eventually reaching 0 before the next Hsync pulse arrives. The

specific value of N varies for different video modes, but is

always less than 255. For example with a 1 μs width Hsync, the

counter only reaches 5 (1 μs/200 ns = 5). Now, when Vsync is

present on the composite sync the counter also counts up.

However, since the Vsync signal is much longer, it counts to a

higher number, M. For most video modes, M is at least 255.

So, Vsync can be detected on the composite sync signal by

detecting when the counter counts to higher than N. The

specific count that triggers detection, T, can be programmed

through the Serial Register 0x11.

Once Vsync has been detected, there is a similar process to

detect when it goes inactive. At detection, the counter first

resets to 0, then starts counting up when Vsync finishes.

Similarly to the previous case, it detects the absence of Vsync

when the counter reaches the threshold count, T. In this way, it

rejects noise and/or serration pulses. Once Vsync is detected to

be absent, the counter resets to 0 and begins the cycle again.

There are two things to keep in mind when using the sync

separator. First, the resulting clean Vsync output is delayed

from the original Vsync by a duration equal to the digital

comparator threshold (N × 200 ns). Second, there is some

variability to the 200 ns multiplier value. The maximum varia-

bility over all operating conditions is ±20% (160 ns to 240 ns).

Since normal Vsync and Hsync pulse widths differ by a factor of

about 500 or more, 20% variability is not an issue.

Hsync Filter and Regenerator

The Hsync filter is used to eliminate any extraneous pulses from

the Hsync or SOGIN inputs, outputting a clean, low-jitter signal

that is appropriate for mode detection and clock generation.

The Hsync regenerator is used to recreate a clean, although not

low jitter, Hsync signal that can be used for mode detection and

counting Hsyncs per Vsync. The Hsync regenerator has a high

degree of tolerance to extraneous and missing pulses on the

Hsync input, but is not appropriate for use by the PLL in

creating the pixel clock because of jitter.

The Hsync regenerator runs automatically and requires no

setup to operate. The Hsync filter requires the setting up of a

filter window. The filter window sets a periodic window of time

around the regenerated Hsync leading edge where valid Hsyncs

are allowed to occur. The general idea is that extraneous pulses

on the sync input occur outside of this filter window and thus

are filtered out. To set the filter window timing, program a value

(x) into Register 0x20. The resulting filter window time is ±x

times 25 ns around the regenerated Hsync leading edge. Just

as for the sync separator threshold multiplier, allow a ±20%

variance in the 25 ns multiplier to account for all operating

conditions (20 ns to 30 ns range).

A second output from the Hsync filter is a status bit (Reg-

ister 0x16[0]) that tells whether extraneous pulses are present

on the incoming sync signal or not. Extraneous pulses are often

included for copy protection purposes; this status bit can be

used to detect that.

The filtered Hsync (rather than the raw Hsync/SOGIN signal)

for pixel clock generation by the PLL is controlled by

raw Hsync/SOGIN signal) for sync processing is controlled by

Hsync is recommended. See Figure 10 for an illustration of a

filtered Hsync.

AD9880/PCB Datasheet(PDF) 18 Page - Analog Devices

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