AD9880SLASHPCB datasheet(47/64 Pages) AD

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AD9880

Rev. 0 | Page 47 of 64

0x28

1-0

Hsync Delay MSBs

Along with the eight bits following these ten bits set

the delay (in pixels) from the Hsync leading edge to

the start of active video. The power-up default setting

is 0x104.

0x29

7-0

Hsync Delay LSBs

See the Hsync Delay MSBs section.

0x2A

3-0

Line Width MSBs

Along with the 8 bits following these 12 bits, set the

width of the active video line (in pixels). The power-

up default setting is 0x500.

0x2B

7-0

Line Width LSBs

See the line width MSBs section.

0x2C

3-0

Screen Height MSBs

Along with the 8 bits following these 12 bits, set the

height of the active screen (in lines). The power-up

default setting is 0x2D0.

0x2D

7-0

Screen Height LSBs

See the Screen Height MSBs section.

0x2E

Ctrl Enable

When set, this bit allows Ctrl [3:0] signals decoded

from the DVI to be output on the I2S data pins. The

power-up default setting is 0.

Table 64. CTRL Enable.

Select

Result

I2S signals on I2S lines

Ctrl [3:0] output on I2S lines

0x2E

6-5

I2S Output Mode

These bits select between four options for the I2S

output: I2S, right-justified, left-justified, or raw

IEC60958 mode. The power-up default setting is 00.

Table 65. I2S Output Select

I2S Output Mode

Result

I2S mode

Right-Justified

Left-Justified

Raw IEC60958 mode

0x2E

4-0

I2S Bit Width

These bits set the I2S bit width for right-justified

mode. The power-up default setting is 24 bits.

0x2F

TMDS Sync Detect

This read-only bit indicates the presence of a TMDS

DE.

Table 66. Detected TMDS Sync Results

Detect

Result

No TMDS DE present

TMDS DE detected

0x2F

TMDS Active

This read only bit indicates the presence of a TMDS

clock.

Table 67. Detected TMDS Clock Results

Detect

Result

No TMDS clock present

TMDS clock detected

0x2F

AV Mute

This read-only bit indicates the presence of AV (audio

video) mute based on general control packets.

Table 68. Detected AV Mute Status

Detect

Result

AV not muted

AV muted

0x2F

HDCP Keys Read

This read-only bit reports if the HDCP keys were read

successfully.

Table 69. HDCP Keys

Detect

Result

Failure to read HDCP keys

HDCP keys read

0x2F

2-0

HDMI Quality

These read-only bits indicate a level of HDMI quality

based on the DE (display enable) edges. A larger

number indicates a higher quality.

0x30

HDMI Content Encrypted

This read-only bit is high when HDCP decryption is

in use (content is protected). The signal goes low

when HDCP is not being used. Customers can use this

bit to determine whether or not to allow copying of

the content. The bit should be sampled at regular

intervals since it can change on a frame by frame

basis.

Table 70. HDCP Activity

Detect

Result

HDCP not in use

HDCP decryption in use

0x30

DVI Hsync Polarity

This read-only bit indicates the polarity of the DVI

Hsync.

AD9880/PCB Datasheet(PDF) 47 Page - Analog Devices

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