MPC8535EBVTATH datasheet(106/126 Pages) FREESCALE

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MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Clocking

Freescale Semiconductor

106

2.23.1

Clock Ranges

Table 73 provides the clocking specifications for the processor cores and Table 74 provides the clocking specifications for the

memory bus.

The DDR memory controller can run in either synchronous or asynchronous mode. When running in synchronous mode, the

memory bus is clocked relative to the platform clock frequency. When running in asynchronous mode, the memory bus is

clocked with its own dedicated PLL. Table 74 provides the clocking specifications for the memory bus.

Table 73. Processor Core Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

600 MHz

800 MHz

1000 MHz

1250 MHz

Min

Max

Min

Max

Min

Max

Min

Max

e500 core processor frequency

600

800

600

1000

600

1250

MHz

1, 2

CCB frequency

400

333

400

333

500

DDR Data Rate

400

500

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” Section 2.23.3, “e500 Core PLL Ratio,“and Section 2.23.4,

“DDR/DDRCLK PLL Ratio,” for ratio settings.

2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency

supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically possible

via valid clock ratio setting in some condition, is not supported.

Table 74. Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

600, 800, 1000, 1250

Min

Max

DDR Memory bus clock speed

200

250

MHz

1, 2, 3, 4

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” Section 2.23.3, “e500 Core PLL Ratio,” and

Section 2.23.4, “DDR/DDRCLK PLL Ratio,” for ratio settings.

2. The Memory bus clock refers to the MPC8535E memory controllers’ MCK[0:5] and MCK[0:5] output clocks, running at half of

the DDR data rate.

3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is

the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,

asynchronous mode must be used.

4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See Section 2.23.4, “DDR/DDRCLK PLL

Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR

data rate.

MPC8535EBVTATH Datasheet(PDF) 106 Page - Freescale Semiconductor, Inc

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