MPC8535EBVTATH datasheet(107/126 Pages) FREESCALE

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Clocking

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

107

2.23.2

CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency

of the CCB is set using the following reset signals, as shown in Table 75:

•

SYSCLK input signal

•

Binary value on LA[28:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values.

2.23.3

e500 Core PLL Ratio

Table 76 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined

by the binary value of LBCTL, LALE and LGPL2 at power up, as shown in Table 76.

2.23.4

DDR/DDRCLK PLL Ratio

The DDR memory controller complex can be synchronous with, or asynchronous to, the CCB, depending on configuration.

Table 77 describes the clock ratio between the DDR memory controller complex and the DDR/DDRCLK PLL reference clock,

DDRCLK, which is not the memory bus clock.

When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default mode of operation

is for the DDR data rate for the DDR controller to be equal to the CCB clock rate in synchronous mode, or the resulting DDR

PLL rate in asynchronous mode.

In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 77 reflects the DDR data rate to DDRCLK ratio,

since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output.

Table 75. CCB Clock Ratio

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

0000

Reserved

1000

8:1

0001

Reserved

1001

9:1

0010

Reserved

1010

10:1

0011

3:1

1011

Reserved

0100

4:1

1100

12:1

0101

5:1

1101

Reserved

0110

6:1

1110

Reserved

0111

Reserved

1111

Reserved

Table 76. e500 Core to CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2 Signals

e500 core: CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2 Signals

e500 core: CCB Clock Ratio

000

4:1

100

2:1

001

9:2

101

5:2

010

Reserved

110

3:1

011

3:2

111

7:2

MPC8535EBVTATH Datasheet(PDF) 107 Page - Freescale Semiconductor, Inc

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