MPC8535EBVTATH datasheet(113/126 Pages) FREESCALE

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System Clocking

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

113

The heat sink removes most of the heat from the device for most applications. Heat generated on the active side of the chip is

conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat

sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance

are the dominant terms.

2.24.3.2

Thermal Interface Materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The

performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is

generally provided by the thermal interface vendors.

Hardware Design Considerations

This section provides electrical and thermal design recommendations for successful application of the MPC8535E.

3.1

System Clocking

This device includes seven PLLs:

•

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio

between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in

Section 2.23.2, “CCB/SYSCLK PLL Ratio.”

•

The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500

core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 2.23.3,

“e500 Core PLL Ratio/”

•

The PCI PLL generates the clocking for the PCI bus

•

The local bus PLL generates the clock for the local bus.

•

There is a PLL for the SerDes1 block to be used for PCI Express interface

•

There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces.

•

The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The

frequency ratio between the DDR clock and DDRCLK is described in Section 2.23.4, “DDR/DDRCLK PLL Ratio.”

3.2

Power Supply Design and Sequencing

3.2.1

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE,

AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). The AVDD level should always be equivalent to VDD, and

preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent

filter circuits per PLL power supply as illustrated in Figure 75, one to each of the AVDD pins. By providing independent filters

to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built

with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.

Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors

of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from

nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 783

FC-PBGA the footprint, without the inductance of vias.

MPC8535EBVTATH Datasheet(PDF) 113 Page - Freescale Semiconductor, Inc

MPC8535EBVTATH Datasheet(HTML) 113 Page - Freescale Semiconductor, Inc

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