PM0215 datasheet(72/91 Pages) STMICROELECTRONICS

72 / 91 page

Core peripherals

PM0215

72/91

Doc ID 022979 Rev 1

4.2.4

Interrupt set-pending register (ISPR)

Address offset: 0x0100

Reset value: 0x0000 0000

This register forces interrupts into pending state, and shows which interrupts are pending.

4.2.5

Interrupt clear-pending register (ICPR)

Address offset: 0x0180

Reset value: 0x0000 0000

Removes pending state from interrupts and shows which interrupts are pending.

SETPEND[31:16]

4321

SETPEND[15:0]

Bits 31:0 SETPEND: Interrupt set-pending bits

Write:

0: No effect

1: Changes interrupt state to pending

Read:

0: Interrupt is not pending

1: Interrupt is pending

Writing 1 to the ISPR bit corresponding to an interrupt that is pending:

–

has no effect.

Writing 1 to the ISPR bit corresponding to a disabled interrupt:

–

sets the state of that interrupt to pending.

CLRPEND[31:16]

rc_w1

4321

CLRPEND[15:0]

rc_w1

Bits 31:0 CLRPEND: Interrupt clear-pending bits

Write:

0: No effect

1: Removes the pending state of an interrupt

Read:

0: Interrupt is not pending

1: Interrupt is pending

Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.

PM0215 Datasheet(PDF) 72 Page - STMicroelectronics

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