PM0215 datasheet(39/91 Pages) STMICROELECTRONICS

39 / 91 page

PM0215

The STM32 Cortex-M0 instruction set

Doc ID 022979 Rev 1

39/91

3.3.4

Address alignment

An aligned access is an operation where a word-aligned address is used for a word, or

multiple word access, or where a halfword-aligned address is used for a halfword access.

Byte accesses are always aligned.

There is no support for unaligned accesses on the Cortex-M0 processor. Any attempt to

perform an unaligned memory access operation results in a HardFault exception.

3.3.5

PC-relative expressions

A PC-relative expression or label is a symbol that represents the address of an instruction or

literal data. It is represented in the instruction as the PC value plus or minus a numeric

offset. The assembler calculates the required offset from the label and the address of the

current instruction. If the offset is too big, the assembler produces an error.

●

For most instructions, the value of the PC is the address of the current instruction plus

four bytes.

●

Your assembler might permit other syntaxes for PC-relative expressions, such as a

label plus or minus a number, or an expression of the form [PC, #number].

3.3.6

Conditional execution

Most data processing instructions can optionally update the condition flags in the application

program status register (APSR) according to the result of the operation (see Application

program status register on page 14). Some instructions update all flags, and some only

update a subset. If a flag is not updated, the original value is preserved. See the instruction

descriptions for the flags they affect.

You can execute an instruction conditionally, based on the condition flags set in another

instruction:

●

Immediately after the instruction that updated the flags

●

After any number of intervening instructions that have not updated the flags

On the Cortex-M0 processor, conditional execution is available by using conditional

branches.

This section describes:

●

The condition flags

●

Condition code suffixes

The condition flags

The APSR contains the following condition flags:

●

N: Set to 1 when the result of the operation is negative, otherwise cleared to 0

●

Z: Set to 1 when the result of the operation is zero, otherwise cleared to 0

●

C: Set to 1 when the operation results in a carry, otherwise cleared to 0.

●

V: Set to 1 when the operation causes an overflow, otherwise cleared to 0.

For more information about the APSR see Program status register on page 13.

PM0215 Datasheet(PDF) 39 Page - STMicroelectronics

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