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MPC8535ECVTATH Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc |
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MPC8535ECVTATH Datasheet(HTML) 66 Page - Freescale Semiconductor, Inc |
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66 / 126 page ![]() MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 enhanced Local Bus Controller (eLBC) Freescale Semiconductor 66 Table 50 provides the DC electrical characteristics for the local bus interface operating at BVDD = 1.8 V DC. 2.12.2 Local Bus AC Electrical Specifications Table 51 describes the general timing parameters of the local bus interface at BVDD = 3.3 V DC. For information about the frequency range of local bus see Section 2.23.1, “Clock Ranges.” Table 50. Local Bus DC Electrical Characteristics (1.8 V DC) Parameter Symbol Condition Min Max Unit Supply voltage 1.8V BVDD — 1.71 1.89 V High-level input voltage VIH —0.65*BVDD 0.3+BVDD V Low-level input voltage VIL — –0.3 0.35*BVDD V Input current (BVIN 1 = 0 V or BV IN = BVDD) IIN — -15 10 μA High-level output voltage VOH IOH = –100 μABVDD – 0.2 — V IOH = –2 mA BVDD – 0.45 — Low-level output voltage VOL IOH = 100 μA— 0.2 V IOH = 2 mA — 0.45 Note: 1. Note that the symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1. Table 51. Local Bus General Timing Parameters (BVDD = 3.3 V DC) Parameter Symbol 1 Min Max Unit Notes Local bus cycle time tLBK 7.5 12 ns 2 Local bus duty cycle tLBKH/tLBK 43 57 % — LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW 150 ps 7 Input setup to local bus clock (except LUPWAIT) tLBIVKH1 1.8 — ns 3, 4 LUPWAIT input setup to local bus clock tLBIVKH2 1.7 — ns 3, 4 Input hold from local bus clock (except LUPWAIT) tLBIXKH1 1.0 — ns 3, 4 LUPWAIT input hold from local bus clock tLBIXKH2 1.0 — ns 3, 4 LALE output transition to LAD/LDP output transition (LATCH setup and hold time) tLBOTOT 1.5 — ns 6 Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 —2.3 ns — Local bus clock to data valid for LAD/LDP tLBKHOV2 —2.4 ns 3 Local bus clock to address valid for LAD tLBKHOV3 —2.3 ns 3 Local bus clock to LALE assertion tLBKHOV4 —2.3 ns 3 Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.7 — ns 3 |
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