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MPC8535ECVTATH Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc |
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MPC8535ECVTATH Datasheet(HTML) 79 Page - Freescale Semiconductor, Inc |
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79 / 126 page ![]() Serial ATA (SATA) MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 79 2.16.1 Requirements for SATA REF_CLK The AC requirements for the SATA reference clock are listed in Table 59. Figure 49. Reference Clock Timing Waveform Table 59. Reference Clock Input Requirements Parameter Symbol Min Typical Max Unit Notes SD2_REF_CLK/_B reference clock cycle time tCLK_REF 100 — 150 MHz 1 SD2_REF_CLK/_B frequency tolerance tCLK_TOL –350 0 +350 ppm — SD_REF_CLK/_B rise/fall time (80%-20%) tCLK_RISE/tCLK_FALL — — 1 ns — SD_REF_CLK/_B duty cycle (@50% X2VDD) tCLK_DUTY 45 50 55 % — SD_REF_CLK/_B cycle to cycle clock jitter (period jitter) tCLK_CJ —— 100 ps — SD_REF_CLK/_B phase jitter (peak-to-peak) tCLK_PJ –50 — +50 ps 2,3 Note: 1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system. 2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps. TH TL Ref_CLK |
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